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HC165 PDF даташит

Спецификация HC165 изготовлена ​​​​«System Logic Semiconductor» и имеет функцию, называемую «8-Bit Serial or Parallel-Input/ Serial-Output Shift Register».

Детали детали

Номер произв HC165
Описание 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register
Производители System Logic Semiconductor
логотип System Logic Semiconductor логотип 

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HC165 Даташит, Описание, Даташиты
SL74HC165
8-Bit Serial or Parallel-Input/
Serial-Output Shift Register
High-Performance Silicon-Gate CMOS
The SL74HC165 is identical in pinout to the LS/ALS165. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device is an 8-bit shift register with complementary outputs
from the last stage. Data may be loaded into the register either in
parallel or in serial form. When the Serial Shift/ Parallel Load input is
low, the data is loaded asynchronously in parallel. When the Serial
Shift/Parallel Load input is high, the data is loaded serially on the rising
edge of either Clock or Clock Inhibit (see the Function Table).
The 2-input NOR clock may be used either by combining two
independent clock sources or by designating one of the clock inputs to
act as a clock inhibit.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
ORDERING INFORMATION
SL74HC165N Plastic
SL74HC165D SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
PIN 16=VCC
PIN 8 = GND
FUNCTION TABLE
Inputs
Internal Stages Output
Serial Shift/ Clock Clock SA A-H QA QB-QG
Parallel Load
Inhibit
QH
L
H
X X a...h a
b-g
h
H
L LX
L QAn-QFn QGn
H
L HX
H QAn-QFn QGn
HL
HL
LX
HX
L QAn-QFn QGn
H QAn-QFn QGn
H X H XX
no change
H H X XX
H L L XX
X = Don’t Care
QAn-QFn = Data shifted from the preceding stage
no change
Operation
Asynchronous Parallel Load
Serial Shift via Clock
Serial Shift via Clock
Inhibit
Inhibited Clock
No Clock
SLS
System Logic
Semiconductor









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HC165 Даташит, Описание, Даташиты
SL74HC165
MAXIMUM RATINGS*
Symbol
VCC
VIN
VOUT
IIN
IOUT
ICC
PD
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Value
-0.5 to +7.0
-1.5 to VCC +1.5
-0.5 to VCC +0.5
±20
±25
±50
750
500
Tstg Storage Temperature
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
-65 to +150
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
Unit
V
V
V
mA
mA
mA
mW
°C
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
VIN, VOUT
TA
tr, tf
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
Min Max Unit
2.0 6.0
V
0 VCC
-55 +125
V
°C
0 1000 ns
0 500
0 400
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND(VIN or VOUT)VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
SLS
System Logic
Semiconductor









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HC165 Даташит, Описание, Даташиты
SL74HC165
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
Symbol
Parameter
Test Conditions
VIH Minimum High-Level VOUT=0.1 V or VCC-0.1 V
Input Voltage
IOUT≤ 20 µA
VIL Maximum Low -Level VOUT=0.1 V or VCC-0.1 V
Input Voltage
IOUT ≤ 20 µA
VOH Minimum High-Level VIN=VIH or VIL
Output Voltage
IOUT ≤ 20 µA
VIN=VIH or VIL
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA
VOL Maximum Low-Level VIN= VIL or VIH
Output Voltage
IOUT ≤ 20 µA
VIN= VIL or VIH
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA
IIN Maximum Input
Leakage Current
VIN=VCC or GND
ICC Maximum Quiescent VIN=VCC or GND
Supply Current
IOUT=0µA
(per Package)
VCC Guaranteed Limit
V 25 °C 85 125 Unit
to °C °C
-55°C
2.0 1.5 1.5 1.5
4.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2
V
2.0 0.3
4.5 0.9
6.0 1.2
0.3 0.3
0.9 0.9
1.2 1.2
V
2.0 1.9
4.5 4.4
6.0 5.9
1.9 1.9
4.4 4.4
5.9 5.9
V
4.5 3.98 3.84 3.7
6.0 5.48 5.34 5.2
2.0 0.1
4.5 0.1
6.0 0.1
0.1 0.1
0.1 0.1
0.1 0.1
V
4.5 0.26 0.33 0.4
6.0 0.26 0.33 0.4
6.0 ±0.1 ±1.0 ±1.0 µA
6.0 8.0
80 160 µA
SLS
System Logic
Semiconductor










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