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PDF C065VL01-V0 Data sheet ( Hoja de datos )
| Número de pieza | C065VL01-V0 | |
| Descripción | COLOR TFT-LCD MODULE | |
| Fabricantes | AUO | |
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Doc. Version
Total Page
Date
0.5
25
2006/11/30
Product Specification
6.5" COLOR TFT-LCD MODULE
MODEL NAME: C065VL01 V0
< >Draft Version
< >Preliminary Specification
< >Final Specification
Note: The content of this specification is subject to change
© 2006 AU Optronics
All Rights Reserved
DO NOT COPY
1 page  
Version
Page:
0.5
5/25
R GB
R GB
……………………………
….
R GB
R GB
……………………………
….
R GB
( 1 2 3….……… ………..…………….2398 2399 2400)
Note 2: The 262K color display depends on 6-bit data signal input.
Note 3: Not including the backlight cable. Refer to Section G, “Outline Dimension” for
further information.
D. Electrical Specifications
1. Pin Assignment
a. TFT-LCD panel driving section
Connector type: FH16-80S-0.3SH or compatible
Pin no Symbol I/O Description
Remark
1
VGH
P Power for LCD
2
DIO2
I/O Start pulse signal
3 AVDD P Analog power for source driver
4 CHNSL1 I Control signal, please set to ‘1’
5 CHNSL0 I Control signal, please set to ‘1’
6
VCC
P Digital power for source driver
7
POL
I Output data polarity control signal
8
REV
I Data inversion control signal output for source driver
9
LINV
I Polarity control signal
10 MUX2 I Source driver control signal
5 Page 
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Page:
0.5
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Parameter
Symbol Min. Typ. Max. Unit
Conditions
CLK frequency
Fclk=1/Tclk - - 45 MHz EDGSL=”0”
CLK frequency
Fclk=1/Tclk - - 22.5 MHz EDGSL=”1”
CLK pulse width
Tcw 6 - - ns
Data set-up time
X1 ~ X5, REV and
Tsu 4 - - ns
DIO1/2 to CLK
Data hold time
Thd 2 - - ns
Propagation delay of DIO1/2
high to low level
Tphl
6 10 15 ns CL=25pF
Propagation delay of DIO1/2
low to high level
Tplh
6 10 15 ns CL=25pF
Time that the last data to LD1 Tld1 1 - - Tclk
LD1 pulse width
Twld1 2 - - Tclk
Time that LD1 to DIO1/2
Tlds 5 - - Tclk
Time that LD1 to LD2
Tld2 2 - - Tclk
LD2 pulse width
Twld2 1 - - Tclk
MUX/LINV/POL setup time Tsu2 6 - - ns
MUX/LINV/POL hold time
Thd2 6 - - ns
Output stable time
Refer to LD2 timing
Tst - - - us
chart
e. Timing Diagrams
Timing Diagram 1 ( CHNSL=”1”, others setting = Default )
<< EDGSL= ”0”, Default >>
CLK
70%
>Thd
70%
Tsu Thd
70%
Tcph
1
70%
30%
>Tsu Tcw Tcw
2
Dio1/2
(input)
Data,
REV
70%
70%
Tsu
70%
Thd 70%
First data Second data
Dio1/2
70% 799
70% 800
Last data
Tplh
Tphl
70%
30%
11 Page | ||
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