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PDF HCC4067B Data sheet ( Hoja de datos )
| Número de pieza | HCC4067B | |
| Descripción | ANALOG MULTIPLEXER/DEMULTIPLEXER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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HCC/HCF4067B
HCC/HCF4097B
ANALOG MULTIPLEXER/DEMULTIPLEXER
4067B–SINGLE 16-CHANNEL
.4097B–DIFFERENTIAL 8-CHANNEL
LOW ON RESISTANCE: 125Ω (typ.) OVER 15
Vp-p SIGNAL INPUT RANGE FOR
VDD - VSS = 15V
. HIGH OFF RESISTANCE: CHANNEL LEAK-
AGE OF ±10pA (typ.) @ VDD - VSS = 10V
. MATCHED SWITCH CHARACTERISTICS:
∆RON = 5Ω (typ.) FOR VDD - VSS = 15V
. VERY LOW QUIESCENT POWER DISSIPA-
TION UNDER A DIGITAL CONTROL INPUT
AND SUPPLY CONDITIONS: 0.2µW (typ.) @
VDD -VSS = 10V
. BINARY ADDRESS DECODING ON CHIP
. QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
. STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
. 5V, 10V AND 15V PARAMETRIC RATINGS
. INPUT CURRENT OF 100nA AT 18V AND 25oC
FOR HCC DEVICE
. 100% TESTED FOR QUIESCENT CURRENT
. MEETS ALL REQUIREMENTS OF JEDECTEN-
TATIVE STANDARD No 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF B
SERIE CMOS DEVICES”
PIN CONNECTIONS
4067B
EY
(Plastic Package)
F
(Ceramic Package)
M1
(Micro Package)
C1
(Chip Carrier)
ORDER CODES :
HCC40XXBF
HCF40XXBM1
HC F 4 0XX BE Y
HCF40XXBC1
4097B
September 1988
1/16
1 page  
HCC/HCF4067B HCC/HCF4097B
TRUTH TABLES FOR HCC/HCF4067B
A
B
C
D
INH
SELECTED
CHANNEL
XX X X 1
None
00000
0
10000
1
01000
2
11000
3
00100
4
10100
5
01100
6
11100
7
00010
8
10010
9
01010
10
11010
11
00110
12
10110
13
01110
14
11110
15
TRUTH TABLE FOR HCC/HCF4097B
A
B
C
INH
SELECTED
CHANNEL
XXX1
None
0 0 00
0X 0Y
1 0 00
1X 1Y
0 1 00
2X 2Y
1 1 00
3X 3Y
0 0 10
4X 4Y
1 0 10
5X 5Y
0 1 10
6X 6Y
1 1 10
7X 7Y
ABSOLUTE MAXIMUM RATING
Symbol
Parameter
Value
Unit
VDD * Supply Voltage: HCC Types
HCF Types
-0.5 to +20
-0.5 to +18
V
V
Vi Input Voltage
-0.5 to VDD + 0.5
V
II DC Input Current (any one input)
± 10 mA
Ptot Total Power Dissipation (per package)
Dissipation per Output Transistor
200 mW
for Top = Full Package Temperature Range
100 mW
Top Operating Temperature: HCC Types
HCF Types
-55 to +125
-40 to +85
oC
oC
Tstg Storage Temperature
-65 to +150
oC
Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress ratingonly and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for external periods may affect device reliability.
* All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
VI
Top
Parameter
Supply Voltage: HCC Types
HCF Types
Input Voltage
Operating Temperature: HCC Types
HCF Types
Value
3 to 18
3 to 15
0 to VDD
-55 to +125
-40 to +85
Unit
V
V
V
oC
oC
5/16
5 Page 
HCC/HCF4067B HCC/HCF4097B
Propagation Delay Waveform Channel Being
Turned ON (RL = 10 KΩ, CL = 50 pF)
Propagation Delay Waveform Channel Being
Turned OFF (RL = 300 Ω, CL = 50 pF)
APPLICATIONS INFORMATION
In applications where separate power sources are
used to drive VDD and the signal inputs, the VDD cur-
rent capability should exceed VDD/RL (RL = effective
external load). This provision avoids permanent cur-
rent flow or clamp action on the VDD supply when
power is applied or removed from the
HCC/HCF4067B or HCC/HCF4097B.
When switching from one address to another, some
of the ON periods of the channels of the multiplexers
will overlap momentarily, which may be objection-
able in certain applications. Also when a channel is
turned ON or OFF by an address input, there is a
momentary conductive path from the channel to
VSS, which will drump some charge from any capa-
citor connected to the input or output of the channel.
The inhibit input turning on a channel will similarly
drump some charge to VSS.
The amount of charge dumped is mostly a function
of the signal level above VSS.
Typically, ay VDD - VSS = 10V, a 100 pF capacitor
connected to the input or output of the channel will
lose 3-4% of its voltage at the moment the channel
turns ON or OFF. This loss of voltage is essentially
independent of the address or inhibit signal trnasi-
tion time, if the transition time is less than 1- 2 µs.
When the inhibit signal turns a channel off, there is
no change dumping of VSS. Rather, there is a slight
rise in the channel voltage level (65 mV typ.) due to
the capacitance coupling from inhibit input to chan-
nel input or output. Address input also couple some
voltage steps onto the channel signal levels.
In certain applications, the external load-resistor
current may include both VDD and signal line com-
ponents. To avoid drawing VDD current when switch
current flows into the transmission gate inputs, the
voltage drop across the bidirectional switch must not
exceed 0.8 V (calculated from RON values shown in
ELECTRICAL CHARACTERISTICS CHART). No
VDD current will flow through RL if the switch current
flows into terminal 1 on the HCC/HCF4067B, termi-
nals 1 and 17 on the HCC/HCF4097B.
11/16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet HCC4067B.PDF ] | |
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