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PDF HM62V8100LBPI-5SL Data sheet ( Hoja de datos )
| Número de pieza | HM62V8100LBPI-5SL | |
| Descripción | 8M SRAM | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HM62V8100LBPI-5SL (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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HM62V8100I Series
Wide Temperature Range Version
8 M SRAM (1024-kword × 8-bit)
ADE-203-1278B (Z)
Rev. 1.0
Mar. 12, 2002
Description
The Hitachi HM62V8100I Series is 8-Mbit static RAM organized 1,048,576-word × 8-bit. HM62V8100I
Series has realized higher density, higher performance and low power consumption by employing Hi-CMOS
process technology. It offers low power standby power dissipation; therefore, it is suitable for battery backup
systems. It is packaged in 48 bumps chip size package with 0.75 mm bump pitch or standard 44-pin TSOP II
for high density surface mounting.
Features
• Single 3.0 V supply: 2.7 V to 3.6 V
• Fast access time: 55 ns (Max)
• Power dissipation:
Active: 6.0 mW/MHz (Typ)
Standby: 1.5 µW (Typ)
• Completely static memory.
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output.
Three state output
• Battery backup operation.
2 chip selection for battery backup
• Temperature range: –40 to +85°C
1 page  
Block Diagram (TSOP)
LSB
A5
A6
A7
A4
A3
A9
A10
A11
A12
A13
MSB A14
HM62V8100I Series
Row
decoder
•
•
•
•
•
Memory matrix
2,048 x 4,096
V CC
V SS
I/O0
I/O7
CS2
CS1
WE
OE
Input
data
control
•
•
Column I/O
Column decoder
•
•
LSB MSB
A16 A17A18 A19A0 A1 A2 A15A8
••
Control logic
5
5 Page 
HM62V8100I Series
Write Cycle
HM62V8100I
-5
Parameter
Symbol Min Max Unit Notes
Write cycle time
tWC 55 — ns
Address valid to end of write
tAW 50 — ns
Chip selection to end of write
tCW 50 — ns 5
Write pulse width
tWP 40 — ns 4
Address setup time
tAS 0 — ns 6
Write recovery time
tWR 0 — ns 7
Data to write time overlap
tDW 25 — ns
Data hold from write time
tDH 0 — ns
Output active from end of write
tOW 5 — ns 2
Output disable to output in High-Z
tOHZ 0 20 ns 1, 2
Write to output in high-Z
tWHZ 0 20 ns 1, 2
Notes: 1. tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions
and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device
and from device to device.
4. A write occures during the overlap of a low CS1, a high CS2, a low WE. A write begins at the latest
transition among CS1 going low, CS2 going high, WE going low. A write ends at the earliest
transition among CS1 going high, CS2 going low, WE going high. tWP is measured from the
beginning of write to the end of write.
5. tCW is measured from the later of CS1 going low or CS2 going high to the end of write.
6. tAS is measured from the address valid to the beginning of write.
7. tWR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write
cycle.
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet HM62V8100LBPI-5SL.PDF ] | |
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