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28F102 Datasheet Download - Catalyst Semiconductor

Номер произв 28F102
Описание CAT28F102
Производители Catalyst Semiconductor
логотип Catalyst Semiconductor логотип 

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28F102 Даташит, Описание, Даташиты
CAT28F102
1 Megabit CMOS Flash Memory
Licensed Intel
second source
FEATURES
s Fast Read Access Time: 45/55/70/90 ns
s Low Power CMOS Dissipation:
–Active: 30 mA max (CMOS/TTL levels)
–Standby: 1 mA max (TTL levels)
–Standby: 100 µA max (CMOS levels)
s High Speed Programming:
–10 µs per byte
–1 Sec Typ Chip Program
s 0.5 Seconds Typical Chip-Erase
s 12.0V ± 5% Programming and Erase Voltage
s Commercial,Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28F102 is a high speed 64K x 16-bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after-sale
code updates. Electrical erasure of the full memory
contents is achieved typically within 0.5 second.
It is pin and Read timing compatible with standard
EPROM and E2PROM devices. Programming and Erase
are performed through an operation and verify algo-
rithm. The instructions are input via the I/O bus, using a
BLOCK DIAGRAM
s 64K x 16 Word Organization
s Stop Timer for Program/Erase
s On-Chip Address and Data Latches
s JEDEC Standard Pinouts:
–40-pin DIP
–44-pin PLCC
–40-pin TSOP
s 100,000 Program/Erase Cycles
s 10 Year Data Retention
s Electronic Signature
two write cycle scheme. Address and Data are latched
to free the I/O bus and address bus during the write
operation.
The CAT28F102 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 40-pin DIP, 44-pin PLCC, or 40-pin TSOP
packages.
I/O0–I/O15
ERASE VOLTAGE
SWITCH
I/O BUFFERS
WE COMMAND
REGISTER
CE
OE
A0–A15
VOLTAGE VERIFY
SWITCH
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
PROGRAM VOLTAGE
SWITCH
CE, OE LOGIC
DATA SENSE
LATCH AMP
Y-DECODER
X-DECODER
1
Y-GATING
1,048,576-BIT
MEMORY
ARRAY
28F101-1
Doc. No. 25038-0A 2/98 F-1







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28F102 Даташит, Описание, Даташиты
CAT28F102
PIN CONFIGURATION
PLCC Package (N)
I/O12
I/O11
I/O10
I/O9
I/O8
VSS
NC
I/O7
I/O6
I/O5
I/O4
6
7
5
4
3
2
1 44 43 42 41 4039
8 38
9 37
10 36
11 35
12 34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
A13
A12
A11
A10
A9
VSS
NC
A8
A7
A6
A5
28F101-2
DIP Package (P)
VPP
CE
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
VSS
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VCC
39 WE
38 NC
37 A15
36 A14
35 A13
34 A12
33 A11
32 A10
31 A9
30 VSS
29 A8
28 A7
27 A6
26 A5
25 A4
24 A3
23 A2
22 A1
21 A0
PIN FUNCTIONS
Pin Name Type
A0–A15
Input
I/O0–I/O15
CE
OE
WE
VCC
VSS
VPP
I/O
Input
Input
Input
NC
Function
Address Inputs for
memory addressing
Data Input/Output
Chip Enable
Output Enable
Write Enable
Voltage Supply
Ground
Program/Erase
Voltage Supply
No Connect
TSOP Package (T14)
A9
A10
A11
A12
A13
A14
A15
NC
WE
VCC
VPP
CE
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VSS
39 A8
38 A7
37 A6
36 A5
35 A4
34 A3
33 A2
32 A1
31 A0
30 OE
29 I/O0
28 I/O1
27 I/O2
26 I/O3
25 I/O4
24 I/O5
23 I/O6
22 I/O7
21 VSS
28F101-3
A0
A1
A2
A3
A4
A5
A6
A7
A8
GND
A9
A10
A11
A12
A13
A14
A15
NC
WE
VCC
Reverse TSOP Package (T14R)
1 40 OE
2 39 I/O0
3 38 I/O1
4 37 I/O2
5 36 I/O3
6 35 I/O4
7 34 I/O5
8 33 I/O6
9 32 I/O7
10 31 GND
11 30 I/O8
12 29 I/O9
13 28 I/O10
14 27 I/O11
15 26 I/O12
16 25 I/O13
17 24 I/O14
18 23 I/O15
19 22 VPP
20 21 CE
28F102 TSOP2
Doc. No. 25038-0A 2/98 F-1
2







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28F102 Даташит, Описание, Даташиты
CAT28F102
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................... –55°C to +95°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ........... –0.6V to +VCC + 2.0V
Voltage on Pin A9 with
Respect to Ground(1) ................... –2.0V to +13.5V
VPP with Respect to Ground
during Program/Erase(1) .............. –0.6V to +14.0V
VCC with Respect to Ground(1) ............ –2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) .................................. 1.0 W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
RELIABILITY CHARACTERISTICS
Symbol
NEND(3)
TDR(3)
VZAP(3)
ILTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
100K
10
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol
CIN(3)
COUT(3)
CVPP(3)
Test
Input Pin Capacitance
Output Pin Capacitance
VPP Supply Capacitance
Limits
Min Max.
6
10
25
Units
pF
pF
pF
Conditions
VIN = 0V
VOUT = 0V
VPP = 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
3 Doc. No. 25038-0A 2/98 F-1










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