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AS29LV800 PDF даташит

Спецификация AS29LV800 изготовлена ​​​​«Alliance Semiconductor» и имеет функцию, называемую «3V 1M x 8/512K x 16 CMOS Flash EEPROM».

Детали детали

Номер произв AS29LV800
Описание 3V 1M x 8/512K x 16 CMOS Flash EEPROM
Производители Alliance Semiconductor
логотип Alliance Semiconductor логотип 

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AS29LV800 Даташит, Описание, Даташиты
March 2001
AS29LV800
®
3V 1M × 8/512K × 16 CMOS Flash EEPROM
Features
• Organization: 1M×8/512K×16
• Sector architecture
- One 16K; two 8K; one 32K; and fifteen 64K byte sectors
- One 8K; two 4K; one 16K; and fifteen 32K word sectors
- Boot code sector architecture—T (top) or B (bottom)
- Erase any combination of sectors or full chip
• Single 2.7-3.6V power supply for read/write operations
• Sector protection
• High speed 70/80/90/120 ns address access time
• Automated on-chip programming algorithm
- Automatically programs/verifies data at specified address
• Automated on-chip erase algorithm
- Automatically preprograms/erases chip or specified
sectors
• Hardware RESET pin
- Resets internal state machine to read mode
• Low power consumption
- 200 nA typical automatic sleep mode current
- 200 nA typical standby current
- 10 mA typical read current
• JEDEC standard software, packages and pinouts
- 48-pin TSOP
- 44-pin SO; availability TBD
• Detection of program/erase cycle completion
- DQ7 DATA polling
- DQ6 toggle bit
- DQ2 toggle bit
- RY/BY output
• Erase suspend/resume
- Supports reading data from or programming data to a
sector not being erased
• Low VCC write lock-out below 1.5V
• 10 year data retention at 150C
• 100,000 write/erase cycle endurance
Logic block diagram
VCC
VSS
RESET
RY/BY
Sector protect/
erase voltage
switches
Erase voltage
generator
DQ0–DQ15
Input/output
buffers
WE
BYTE
Program/erase
control
Command
register
CE
OE
A-1
Program voltage
generator
Chip enable
Output enable
Logic
STB Data latch
STB Y decoder
Y gating
VCC detector
Timer
A0–A18
X decoder
Cell matrix
Pin arrangement
48-pin TSOP
AS29LV800
44-pin SO
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 RESET
43 WE
42 A8
41 A9
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
33 BYTE
32 VSS
31 DQ15/A-1
30 DQ7
29 DQ14
28 DQ6
27 DQ13
26 DQ5
25 DQ12
24 DQ4
23 VCC
Selection guide
Maximum access time
Maximum chip enable access time
Maximum output enable access time
* Regulated voltage range of 3.0 to 3.6V
tAA
tCE
tOE
29LV800-70R*
70
70
30
29LV800-80
80
80
30
29LV800-90
90
90
35
29LV800-120
120
120
50
Unit
ns
ns
ns
3/22/01; V.1.0
Alliance Semiconductor
P. 1 of 25
Copyright © Alliance Semiconductor. All rights reserved.









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AS29LV800 Даташит, Описание, Даташиты
March 2001
AS29LV800
®
Functional description
The AS29LV800 is an 8 megabit, 3.0 volt Flash memory organized as 1 Megabyte of 8 bits/512Kbytes of 16 bits each. For
flexible erase and program capability, the 8 megabits of data is divided into nineteen sectors: one 16K, two 8K, one 32K, and
fifteen 64k byte sectors; or one 8K, two 4K, one 16K, and fifteen 32K word sectors. The ×8 data appears on DQ0–DQ7; the
×16 data appears on DQ0–DQ15. The AS29LV800 is offered in JEDEC standard 48-pin TSOP and 44-pin SOP packages. This
device is designed to be programmed and erased in-system with a single 3.0V VCC supply. The device can also be
reprogrammed in standard EPROM programmers.
The AS29LV800 offers access times of 70/80/90/120 ns, allowing 0-wait state operation of high speed microprocessors. To
eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. Word
mode (×16 output) is selected by BYTE = high. Byte mode (×8 output) is selected by BYTE = low.
The AS29LV800 is fully compatible with the JEDEC single power supply Flash standard. Write commands are sent to the
command register using standard microprocessor write timings. An internal state-machine uses register contents to control the
erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase
operations. Read data from the device occurs in the same manner as other Flash or EPROM devices. Use the program command
sequence to invoke the automated on-chip programming algorithm that automatically times the program pulse widths and
verifies proper cell margin. Use the erase command sequence to invoke the automated on-chip erase algorithm that
preprograms the sector (if it is not already programmed before executing the erase operation), times the erase pulse widths,
and verifies proper cell margin.
Boot sector architecture enables the system to boot from either the top (AS29LV800T) or the bottom (AS29LV800B) sector.
Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other
sectors. A sector typically erases and verifies within 1.0 seconds. Hardware sector protection disables both program and erase
operations in all, or any combination of, the nineteen sectors. The device provides true background erase with Erase Suspend,
which puts erase operations on hold to either read data from, or program data to, a sector that is not being erased. The chip
erase command will automatically erase all unprotected sectors.
A factory shipped AS29LV800 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is programmed into
the array one byte at a time in any sequence and across sector boundaries. A sector must be erased to change bits from 0 to 1.
Erase returns all bytes in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on other
sectors.
The device features single 3.0V power supply operation for Read, Write, and Erase functions. Internally generated and
regulated voltages are provided for the Program and Erase operations. A low VCC detector automatically inhibits write
operations during power transtitions. The RY/BY pin, DATA polling of DQ7, or toggle bit (DQ6) may be used to detect end of
program or erase operations. The device automatically resets to the read mode after program/erase operations are completed.
DQ2 indicates which sectors are being erased.
The AS29LV800 resists accidental erasure or spurious programming signals resulting from power transitions. Control register
architecture permits alteration of memory contents only after successful completion of specific command sequences. During
power up, the device is set to read mode with all program/erase commands disabled when VCC is less than VLKO (lockout
voltage). The command registers are not affected by noise pulses of less than 5 ns on OE, CE, or WE. To initiate write
commands, CE and WE must be logical zero and OE a logical 1.
When the device’s hardware RESET pin is driven low, any program/erase operation in progress is terminated and the internal
state machine is reset to read mode. If the RESET pin is tied to the system reset circuitry and a system reset occurs during an
automated on-chip program/erase algorithm, data in address locations being operated on may become corrupted and requires
rewriting. Resetting the device enables the system’s microprocessor to read boot-up firmware from the Flash memory.
The AS29LV800 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes are
programmed one at a time using EPROM programming mechanism of hot electron injection.
3/22/01; V.1.0
Alliance Semiconductor
P. 2 of 25









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AS29LV800 Даташит, Описание, Даташиты
March 2001
AS29LV800
®
Operating modes
Mode
CE OE WE A0 A1 A6
ID read MFR code
L
L
HL
L
L
ID read device code L L H H L L
Read L L H A0 A1 A6
Standby
HX X X X X
Output disable
L HHX X X
Write
L H L A0 A1 A6
Enable sector protect L
VID Pulse/L L
HL
Sector unprotect L VID Pulse/L L H H
Temporary sector
unprotect
X
X
X
X
X
X
Verify sector protectL L H L H L
Verify sector unprotectL L H L H H
Hardware Reset
XXXXXX
L = Low (<VIL) = logic 0; H = High (>VIH) = logic 1; VID = 10.0 ± 1.0V; X = don’t care.
In ×16 mode, BYTE = VIH. In ×8 mode, BYTE = VIL with DQ8-DQ14 in high Z and DQ15 = A-1.
Verification of sector protect/unprotect during A9 = VID.
A9 RESET DQ
VID H
VID H
A9 H
XH
Code
Code
DOUT
High Z
X H High Z
A9 H
VID H
VID H
DIN
X
X
X VID X
VID H
VID H
XL
Code
Code
High Z
Mode definitions
Item Description
ID MFR code,
device code
Read mode
Standby
Selected by A9 = VID(9.5V–10.5V), CE = OE = A1 = A6 = L, enabling outputs.
When A0 is low (VIL) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products.
When A0 is high (VIH), DOUT represents the device code for the AS29LV800.
Selected with CE = OE = L, WE = H. Data is valid in tACC time after addresses are stable, tCE after CE is low
and tOE after OE is low.
Selected with CE = H. Part is powered down, and ICC reduced to <1.0 µA when CE = VCC ± 0.3V = RESET. If
activated during an automated on-chip algorithm, the device completes the operation before entering
standby.
Output disable Part remains powered up; but outputs disabled with OE pulled high.
Write
Selected with CE = WE = L, OE = H. Accomplish all Flash erasure and programming through the command
register. Contents of command register serve as inputs to the internal state machine. Address latching occurs
on the falling edge of WE or CE, whichever occurs later. Data latching occurs on the rising edge WE or CE,
whichever occurs first. Filters on WE prevent spurious noise events from appearing as write commands.
Enable
sector protect
Hardware protection circuitry implemented with external programming equipment causes the device to
disable program and erase operations for specified sectors. For in-system sector protection, refer to Sector
protect algorithm on page 14.
Sector
unprotect
Disables sector protection for all sectors using external programming equipment. All sectors must be
protected prior to sector unprotection. For in-system sector unprotection, refer to Sector unprotect algorithm
on page 14.
Verify sector
protect/
unprotect
Verifies write protection for sector. Sectors are protected from program/erase operations on commercial
programming equipment. Determine if sector protection exists in a system by writing the ID read command
sequence and reading location XXX02h, where address bits A12–18 select the defined sector addresses. A
logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector.
3/22/01; V.1.0
Alliance Semiconductor
P. 3 of 25










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