NTE7483 PDF даташит
Спецификация NTE7483 изготовлена «NTE Electronics» и имеет функцию, называемую «TTL - 4-Bit Binary Full Adder». |
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Детали детали
Номер произв | NTE7483 |
Описание | TTL - 4-Bit Binary Full Adder |
Производители | NTE Electronics |
логотип |
4 Pages
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NTE7483
Integrated Circuit
TTL − 4−Bit Binary Full Adder with Fast Carry
Description:
The NTE7483 is a 4−bit binary full adder in a 16−Lead plastic DIP type package that performs the addition
of two 4−bit binary numbers. The sum () outputs are provided for each bit and the resultant carry (C4) is
obtained from the fourth bit. This device features full internal look−ahead across all four bits generating the
carry term in ten nanoseconds (typ). This capability provides the system designer with partial look−ahead
performance at the economy and reduced package count of a ripply−carry implementation.
The adder logic, including the carry, is implemented in its true form. End around carry can be accomplished
without the need for logic or level inversion.
Features:
D Full−Carry Look−Ahead Across the Four Bits
D Systems Achieve Partial Look−Ahead Performance with the Economy of Ripple−Carry
D The NTE74283 is Recommended for New Design as it Features Supply Voltage and GND on
Corner Pins to Simplify Board Layout.
Absolute Maximum Ratings: (Note 1)
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Interemitter Voltage (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65C to +150C
Note 1. Unless otherwise specified, all voltages are referenced to GND.
Note 2. This is the voltage between two emitters of a multiple−emitter transistor. This rating applies
between the following pairs: A1 and B1, A and B2, A3 and B3, A4 and B4.
Recommended Operating Conditions:
Parameter
Supply Voltage
High−Level Output Current
Any Output Except C4
Output C4
Low−Level Output Current
Any Output Except C4
Output C4
Operating Temperature Range
Symbol
VCC
IOH
IOL
TA
Min Typ Max Unit
4.75 5.0 5.25 V
− − −800 A
− − −400 A
− − 16 mA
− − 8 mA
0 − +70 C
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Electrical Characteristics: (Note 3, Note 4)
Parameter
Symbol
Test Conditions
High Level Input Voltage
VIH
Low Level Input Voltage
VIL
Input Clamp Voltage
VIK VCC = MIN, II = −12mA
High Level Output Voltage
VOH VCC = MIN, VIH = 2V, VIL = 0.8V, IOH = MAX
Low Level Output Voltage
VOL VCC = MIN, VIH = 2V, VIL = 0.8V, IOL = 4mA
Input Current
II VCC = MAX, VI = 5.5V
High Level Input Current
IIH VCC = MAX, VI = 2.4V
Low Level Input Current
IIL VCC = MAX, VI = 0.4V
Short−Circuit Output Current
Any Output Except C4
IOS
VCC = MAX, Note 5
Output C4
Supply Current
ICC VCC = MAX, Outputs Open
All B Low, Other Inputs at 4.5V
All Inputs at 4.5V
Min Typ Max Unit
2 − −V
− − 0.8 V
− − −1.5 V
2.4 3.4 −
V
− 0.2 0.4 V
− − 1 mA
− − 40 A
− − −1.6 mA
−18 − −55 mA
−18 − −70 mA
− 56 − mA
− 66 110 mA
Note 3. .For conditions shown as MIN or MAX, use the appropriate value specified under “Recommended
Operation Conditions”.
Note 4. All typical values are at VCC = 5V, TA = +25C.
Note 5. Not more than one output should be shorted at a time.
Switching Characteristics: (VCC = 5V, RL = 667, TA = +25C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Propagation Delay Time
(From C0 Input to Any Output)
tPLH
tPHL
RL = 400, CL = 15pF
− 14 21 ns
− 12 21 ns
Propagation Delay Time
(From Ai or Bi Input to i Output)
tPLH
tPHL
− 16 24 ns
− 16 24 ns
Output Enable Time
(From C0 Input to C4 Output)
tPZH
tPZL
RL = 780, CL = 15pF
− 9 14 ns
− 11 16 ns
Propagation Delay Time
(From Ai or Bi Input to C4 Output)
tPLH
tPHL
− 9 14 ns
− 11 16 ns
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Function Table:
Output
Input
When
C0 = L
When
C2 = L
When
C0 = H
When
C2 = H
A1
B1
A3
A2
B3
B2
A4
B4 S1
S3 S2
C2
S4
C4 S1
S3 S2
C2
S4
C4
L L L L L L LHL L
HL L LHL L LHL
LHL LHL L LHL
HHL L LHLHHL
L LHL LHLHHL
HLHLHHL L LH
LHHLHHL L LH
HHHL L LHHLH
L L LHLHLHHL
HL LHHHL L LH
LHLHHHL L LH
HHLHL LHHLH
L LHHL LHHLH
H L HHH L H L HH
L HHHH L H L HH
HHHH L HHHHH
H = HIGH Level
L = LOW Level
NOTE: Input conditions at A1, B1, A2, B2, and C0 are used to determine outputs 1 and 2 and the
value of the internal carry C2. The values at C2, A3, B3, A4, and B4 are then used to determine outputs
3, 4, and C4.
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