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PDF HD64F36037G Data sheet ( Hoja de datos )
| Número de pieza | HD64F36037G | |
| Descripción | 16-Bit Single-Chip Microcomputer | |
| Fabricantes | Renesas | |
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REJ09B0026-0400
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
16 ,H8/36057Group H8/36037Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8 Family/H8/300H Tiny Series
H8/36057
H8/36054
H8/36037
H8/36036
H8/36035
H8/36034
H8/36033
H8/36032
HD64F36057,
HD64336057,
HD64F36054,
HD64336054,
HD64F36037,
HD64336037,
HD64336036,
HD64336035,
HD64F36034,
HD64336034,
HD64336033,
HD64336032,
HD64F36057G
HD64336057G
HD64F36054G
HD64336054G
HD64F36037G
HD64336037G
HD64336036G
HD64336035G
HD64F36034G
HD64336034G
HD64336033G
HD64336032G
Rev.4.00
Revision Date: Mar. 15, 2006
1 page  
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 4.00 Mar. 15, 2006 Page v of xxxii
5 Page 
6.2 Mode Transitions and States of LSI.................................................................................... 82
6.2.1 Sleep Mode ......................................................................................................... 84
6.2.2 Standby Mode ..................................................................................................... 84
6.2.3 Subsleep Mode.................................................................................................... 85
6.2.4 Subactive Mode .................................................................................................. 85
6.3 Operating Frequency in Active Mode................................................................................. 86
6.4 Direct Transition ................................................................................................................. 86
6.4.1 Direct Transition from Active Mode to Subactive Mode.................................... 86
6.4.2 Direct Transition from Subactive Mode to Active Mode.................................... 87
6.5 Module Standby Function................................................................................................... 87
Section 7 ROM ....................................................................................................89
7.1 Block Configuration ........................................................................................................... 89
7.2 Register Descriptions.......................................................................................................... 91
7.2.1 Flash Memory Control Register 1 (FLMCR1).................................................... 91
7.2.2 Flash Memory Control Register 2 (FLMCR2).................................................... 92
7.2.3 Erase Block Register 1 (EBR1) .......................................................................... 93
7.2.4 Flash Memory Power Control Register (FLPWCR) ........................................... 94
7.2.5 Flash Memory Enable Register (FENR) ............................................................. 94
7.3 On-Board Programming Modes.......................................................................................... 95
7.3.1 Boot Mode .......................................................................................................... 96
7.3.2 Programming/Erasing in User Program Mode.................................................... 98
7.4 Flash Memory Programming/Erasing............................................................................... 100
7.4.1 Program/Program-Verify .................................................................................. 100
7.4.2 Erase/Erase-Verify............................................................................................ 103
7.4.3 Interrupt Handling when Programming/Erasing Flash Memory....................... 103
7.5 Program/Erase Protection ................................................................................................. 105
7.5.1 Hardware Protection ......................................................................................... 105
7.5.2 Software Protection........................................................................................... 105
7.5.3 Error Protection................................................................................................. 105
7.6 Programmer Mode ............................................................................................................ 106
7.7 Power-Down States for Flash Memory............................................................................. 106
Section 8 RAM ..................................................................................................109
Section 9 I/O Ports .............................................................................................111
9.1 Port 1................................................................................................................................. 111
9.1.1 Port Mode Register 1 (PMR1) .......................................................................... 112
9.1.2 Port Control Register 1 (PCR1) ........................................................................ 113
9.1.3 Port Data Register 1 (PDR1)............................................................................. 113
Rev. 4.00 Mar. 15, 2006 Page xi of xxxii
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HD64F36037G.PDF ] | |
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