CCD525 PDF даташит
Спецификация CCD525 изготовлена «Fairchild Imaging» и имеет функцию, называемую «Time Delay Integration Line Scan Sensor». |
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Детали детали
Номер произв | CCD525 |
Описание | Time Delay Integration Line Scan Sensor |
Производители | Fairchild Imaging |
логотип |
6 Pages
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CCD525
Time Delay Integration
Line Scan Sensor
FEATURES
2048 Active Pixels Per Line
96 TDI Lines
13µm x13 µm Pixels
4 High Speed Output Ports
TDI Stages Selectable Between 96, 64, 48,
32, or 24
100 MHz Data Rate with 4 Outputs
Operating at 25 MHz
42 kHz Line Rate
2000X Antiblooming Protection
High Sensitivity
RoHS Compliant
GENERAL DESCRIPTION
The CCD525 is a Time Delay Integration (TDI)
sensor designed for a wide range of imaging
applications requiring high speed operation
combined with high sensitivity. The sensor is
capable of producing a total data rate of 100 MHz
(line rate > 42 kHz). The CCD has a total imaging
area of 2048 contiguous elements by 96 TDI rows.
The pixel dimensions are 13µm by 13µm. The
CCD overall dimensions are 27.940 mm x 3.302
mm. The sensor is mounted in a custom 40-pin
dual-in-line ceramic package.
The CCD525 imaging area is controlled by 3-
phase timing, and exposure control is performed
by selecting the number of active TDI stages.
Independent TDI control gates allow the following
number of TDI stages to be selected: 96, 64, 48,
32, or 24. The CCD525 features lateral anti-
blooming structures capable of 2000X over-
saturation protection.
The vertical (parallel) imaging register is
separated from the horizontal (serial) registers by
50 isolation rows. The isolation rows are also
controlled by 3-phase timing. The isolation rows
are covered with a light shield and are used to
transfer the charge from the imaging area to four
horizontal registers. The horizontal registers are
controlled by 4-phase timing. The design of the
horizontal registers has been optimized for high
charge transfer efficiency at low signal levels.
Each horizontal register is connected to a high
speed output amplifier. The output amplifier is a
three-stage source follower designed for high
conversion gain and extended bandwidth.
DEVICE ARCHITECTURE
The CCD525 operates in buried channel mode for
optimal performance. The imaging area consists
of 2048 contiguous pixels by 96 rows.
Photogenerated charge is integrated in this
region, then following the integration time, the
charge is transferred line by line to the adjacent
isolation rows for readout. The number of active
TDI rows is simply controlled by biasing the
appropriate control gates, VSWxx, low. Normal
vertical timing is employed across the array
irrespective of the selected number of active TDI
stages. The last gate in the vertical register is also
called the vertical transfer gate, ΦX. The charge is
transferred from the vertical register to the
horizontal registers when ΦX is clocked low. The
horizontal registers require 4-phase timing.
Charge is transferred, pixel by pixel, to the floating
diffusion sense node where it produces a voltage
change corresponding to the signal level. After the
signal is sampled, the reset gate is clocked high
to clear the signal, and restore the potential of the
sense node to the VRD reset drain voltage. There
are 3 prescan elements in each video line.
Fairchild Imaging • 1801 McCarthy Blvd. • Milpitas CA 95035 USA • (800) 325-6975 • Rev A • Page 1 of 6
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V1
V2
V3
CCD525 Block Diagram
PACKAGE INFORMATION
The CCD525 is mounted in a ceramic dual-in-line
package with 40 pins. The spacing between
each pin is 0.100”, and the distance between the
two rows of pins is 0.800”. The overall
dimensions of the package are 2.000” x 0.810” x
0.130”. The package window is covered with an
antireflection (AR) coated cover glass.
CCD525 Package Drawing
Fairchild Imaging • 1801 McCarthy Blvd. • Milpitas CA 95035 USA • (800) 325-6975 • Rev A • Page 2 of 6
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PACKAGE PIN ASSIGNMENT
CCD525 Package
pinout diagram
(TOP VIEW)
40
PIN NAME AND DESCRIPTION
Pin Pin Name
Description
Pin Pin Name
Description
1 ΦR
Reset gate
40 H3
Horizontal CCD clock phase 3
2 VSS
Substrate
39 H1
Horizontal CCD clock phase 1
3 N/C
No connect
38 H2
Horizontal CCD clock phase 2
4 VRD1
Output 1 reset drain 37 H4
Horizontal CCD clock phase 4
5 VDD
Amplifier supply
36 ΦX
Vertical transfer gate
6 Vout1
Video output 1
35 VLS
Light shield ground
7 VOG
Output gate
34 V1
Vertical CCD clock phase 1
8 N/C
No connect
33 N/C
No connect
9 VRD2
Output 2 reset drain 32 VSW24 TDI 24 select gate
10 N/C
No connect
31 V2
Vertical CCD clock phase 2
11 Vout2
Video output 2
30 VSW32 TDI 32 select gate
12 VSG
Amplifier supply return 29 VSW48 TDI 48 select gate
13 Vbias
Current source bias 28 V3
Vertical CCD clock phase 3
14 N/C
No connect
27 VSW64 TDI 64 select gate
15 VRD3
Output 3 reset drain 26 N/C
No connect
16 Vout3
Video output 3
25 VSKG
Overflow gate bias
17 VDD
Amplifier supply
24 Vsink
Overflow drain bias
18 N/C
No connect
23 ΦX
Vertical transfer gate
19 VRD4
Output 4 reset drain 22 ΦR
Reset clock
20 Vout4
Video output 4
21 VSS
Substrate
Fairchild Imaging • 1801 McCarthy Blvd. • Milpitas CA 95035 USA • (800) 325-6975 • Rev A • Page 3 of 6
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Номер в каталоге | Описание | Производители |
CCD525 | Time Delay Integration Line Scan Sensor | Fairchild Imaging |
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