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PDF CCD8091 Data sheet ( Hoja de datos )
| Número de pieza | CCD8091 | |
| Descripción | 9K x 128 Element Delay and Integration Sensor | |
| Fabricantes | Fairchild Imaging | |
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CCD8091
9K x 128 Element
TDI – Time, Delay and Integration Sensor
FEATURES
• 9216 pixels per line
• Number of TDI stages electronically
selectable: {4, 8, 16, 32, 64, 96, 128}
• Bi-directional TDI (shift up or down)
• 6 outputs — each capable of 20MHz data
rate — 160MHz total data rate
• 100% fill factor
• 8.75µm x 8.75µm pixel size
• On-chip binning capability
GENERAL DESCRIPTION
The CCD8091 is a 9216 pixel x 128 line,
high speed TDI sensor. The active imaging
area is organized as 9216 vertical columns
and 128 horizontal TDI rows. The array is
set up for bi-directional operation. There are
identical output registers and amplifiers on
both the top and the bottom of the array.
The outputs to be used (either top or
bottom) are user-selectable and controlled
by the vertical clock timing. In addition, the
exposure level can be controlled by reducing
the number of TDI rows from 128 to 96, 64,
32, 16, 8 or 4. This is also user-selectable
and is accomplished by supplying the
appropriate phasing for the vertical clocks
within each section. For instance, if 64 lines
of TDI were required, the vertical clocks for
lines 65-128 would be connected to a high
potential, which would drain these unused
rows out to the opposite side (unused) of the
array to be dumped into the VOFD drain.
With six outputs, each running at 20MHz,
the CCD8091 can provide a total data rate
of 120MHz enabling the CCD to run at better
than 12kHz line rate. Utilizing Fairchild
Imaging proprietary buried channel CCD
process, the CCD8091 achieves consistent,
superior TDI performance.
The active imaging area is separated from
the six horizontal output registers by 21
isolation rows. These isolation rows are
covered by a metal lightshield to protect
them while charge transfers to the output
registers. Both the active imaging area and
the isolation region utilize 3-phase clocking.
The six horizontal output registers utilize 4-
phase clocking. Special design techniques
have been implemented to maximize charge
transfer efficiency especially at low light
levels. The output amplifier is a 3-stage
source follower configuration. This allows
maximum scale factor (charge to voltage
conversion) and maximum bandwidth.
The CCD8091 is housed in a custom 176
pin (100 mil grid) ceramic PGA package. It
has an AR coated window.
FUNCTIONAL DESCRIPTION
The following functional elements are
illustrated in the block diagram:
Image Sensing Elements: These are
elements of a line of 9216 image sensors
separated by channel stops and covered by
a passivation layer. Incident photons pass
through a transparent polycrystalline silicon
gate structure creating electron hole pairs.
The resulting photoelectrons are collected in
the photosites during the integration period.
The amount of charge accumulated in each
photosite is a linear function of the localized
incident illumination intensity and integration
period.
Transfer Gates: This gate is a structure
adjacent to the row of image sensor
elements. The charge packets accumulated
in the photosites are transferred in parallel
via the transfer gate to the transport shift
1801 McCarthy Blvd.• Milpitas CA 95035 • (800) 325-6975 • Fax (408) 435-7352 • www.fairchildimaging.com • Rev B • 1 of 24
1 page  
CCD8091
9K x 128 Element
TDI—Time, Delay and Integration Sensor
Block Diagram at Sector T1 Output Amplifier
(All top sectors T1, T2, …T8 have this design.)
VOFD-T1
overflow gate
VOFD-T1
overflow gate
VOFD-T1
overflow gate
φR-T1
VRD-T1
VDD-T1
H3 H4 H1 H2 H3 H4 H1 H2 H3 H4 H1 H2 H3 H4 φOG VOG
-T1 -T1 -T1 -T1 -T1 -T1 -T1 -T1 -T1 -T1 -T1 -T1 -T1 -T1 -T1 -T1
1 pixel up
(8.75µm)
H1-T1
VTG-T
V1HS-T
V2HS-T
V3HS-T
V1HS-T
V2HS-T
V3HS-T
V1HS-T
V2HS-T
V3X-T
V1X-T
V2X-T
V3X-T
V1X-T
V2X-T
V3X-T
V1X-T
V2X-T
V3X-T
V1X-T
V2X-T
VSW128-D
V1A-T
V2A-T
V3A-T
V1A-T
V2A-T
V3A-T
V1A-T
V2A-T
V3A-T
V1A-T
V2A-T
VSW4-U
V1C-T
V2C-T
V3C-T
V1C-T
V2C-T
V3C-T
V1C-T
V2C-T
VSW8-U
V1D-T
V2D-T
H1-T1
VTG-T
V1HS-T
V2HS-T
V3HS-T
V1HS-T
V2HS-T
V3HS-T
V1HS-T
V2HS-T
V3X-T
V1X-T
V2X-T
V3X-T
V1X-T
V2X-T
V3X-T
V1X-T
V2X-T
V3X-T
V1X-T
V2X-T
VSW128-D
V1A-T
V2A-T
V3A-T
V1A-T
V2A-T
V3A-T
V1A-T
V2A-T
V3A-T
V1A-T
V2A-T
VSW4-U
V1C-T
V2C-T
V3C-T
V1C-T
V2C-T
V3C-T
V1C-T
V2C-T
VSW8-U
V1D-T
V2D-T
H1-T1
VTG-T
V1HS-T
V2HS-T
V3HS-T
V1HS-T
V2HS-T
V3HS-T
V1HS-T
V2HS-T
V3X-T
V1X-T
V2X-T
V3X-T
V1X-T
V2X-T
V3X-T
V1X-T
V2X-T
V3X-T
V1X-T
V2X-T
VSW128-D
V1A-T
V2A-T
V3A-T
V1A-T
V2A-T
V3A-T
V1A-T
V2A-T
V3A-T
V1A-T
V2A-T
VSW4-U
V1C-T
V2C-T
V3C-T
V1C-T
V2C-T
V3C-T
V1C-T
V2C-T
VSW8-U
V1D-T
V2D-T
VGT-T1
VSRC-T1
VOUT-T1
RLOAD-T1
VSS
3 “high-speed” (<5% duty-cycle clocks)
opaqued readout rows
18 “low-speed” (~50% duty-cycle clocks)
opaqued readout rows
(most of light shield is not
shown on this sketch)
Opaque light shield edge
Switch gate to select TDI-128 down
TDI transfer
Up
4 “low-speed” (~50% duty-cycle clocks) pixel rows
Switch gate to select TDI-4 up
4 “low-speed” (~50% duty-cycle clocks) pixel rows
Switch gate to select TDI-8 up
pixel col. #3
pixel col. #2
pixel col. #1
1801 McCarthy Blvd.• Milpitas CA 95035 • (800) 325-6975 • Fax (408) 435-7352 • www.fairchildimaging.com • Rev B • 5 of 24
5 Page 
CCD8091
9K x 128 Element
TDI—Time, Delay and Integration Sensor
Name
V1, V2
V3
V1-HS,
V2-HS,
V3-HS
H1
H2, H3,
H4
φOG
(FOG)
φR
(RG)
Clock Voltages
Parameter
Min Typ Max Unit Remarks
“Slow” (~50% duty cycle) vertical shift register clocks
Clock-High +18 V Readout side
Clock-Low
0 V Readout side
V-dump
+15 V Dump side
“Slow” (~50% duty cycle) vertical shift register clock
Clock-High +18 V Readout side
Clock-Low
0 V Readout side
V-dump
V-off
+15 V Dump side
-3 V For VSWxx TDI-length-control gate at the
selected readout/dump boundary
“Fast” (<5% duty cycle) vertical shift register clocks (3 isolation rows nearest Horizontal shift registers)
Clock-High +15 V Readout side
Clock-Low
V-dump
0 V Readout side
+15 V Dump side
Horizontal shift register clock, and Vertical→Horizontal transfer clock
Trilevel
+5 V Only during V→H transfer
Clock-High
0 V Note 1
Clock-Low
-5 V Note 1
H-dump
+3 V Dump side
Horizontal shift register clocks
Clock-High
0 V Note 1
Clock-Low
-5 V Note 1
H-dump
+3 V Dump side
Clocked output gate
Clock-High +1 V Note 1
Clock-Low
-5 V Note 1
H-dump
+3 V Dump side (or set to φOG clock-high)
Reset gate clock
Clock-High +15 V
Clock-Low
+4 V
H-dump
+3 V Dump side (or set to φR clock-high)
Note 1: May require individually tuned voltages for optimum performance, especially at high speed.
1801 McCarthy Blvd.• Milpitas CA 95035 • (800) 325-6975 • Fax (408) 435-7352 • www.fairchildimaging.com • Rev B • 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet CCD8091.PDF ] | |
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