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PDF GM16C550 Data sheet ( Hoja de datos )
| Número de pieza | GM16C550 | |
| Descripción | ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFOs | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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GM16C550
GM16C550
ASYNCHRONOUS COMMUNICATIONS
ELEMENT WITH FIFOs
Descriptions
The GM16C550 is an asynchronous communi-
cations element (ACE) that is functionally
equivalent to the GM16C450, and addition-ally
incorporates a 16byte FIFOs are available on both
the transmitter and receiver, and can be activated by
placing the device in the FIFO mode. After a reset,
the registers of the GM16C550 are identical to those
of the GM16C450.
The UART performs serial-to-parallel conver- sion
on data characters received from a peri-pheral
device or a MODEM, and parallel-to- serial
conversion on data characters received from the
CPU. The CPU can read the com- plete status of
the UART at any time during the functional
operation. Status information reported includes the
type and condition of the transfer operations
being performed by the UART, as well as any
error conditions (parity, overrun, framing, or break
interrupt).
Pin Configulation
Features
l Fully compatible with GM16C450.
l Modem controm signals include CTS , RTS ,
DSR , DTR , RI and - DCD .
l Programmable serial characteristics:
—5-, 6-, 7- or 8-bit characters
— Even-, odd-, or no-parity bit generation and
detection
—1-, 11/2- or 2-stop bit generation
— Baud rate generation (DC to 256K baud)
l 16 byte FIFO reduces CPU interrupts.
l Independent control of transmit, receive, line
status, data set interrupts, FIFOs.
l Full status reporting capabilities
l Three-state, TTL drive capabilities for bi-
derectional data bus and control bus.
l 40DIP/44PLCC
D0
D1
D2
D3
D4
D5
D6
D7
RCLK
SIN
SOUT
CS0
CS1
CS2
BAUDQUT
XTAL1
XTAL2
DOSTR
DOSTR
VSS
VCC
RI
DCD
DSR
CTS
MR
OUT1
DTR
RTS
OUT2
INTRPT
RXRDY
A0
A1
A2
ADS
TXRDY
DDIS
DISTR
DISTR
D5
D6
D7
RCLK
SIN
N.C.
SOUT
CS0
CS1
CS2
BAUDQUT
MR
OUT1
DTR
RTS
OUT2
N.C.
INTRPT
RXRDY
A0
A1
A2
1
1 page  
GM16C550
Timing Waveforms (All timings are referenced to valid 0 and valid)
External Clock Input (8.0 MHz Max.)
2.4V
XIN
t XH
2.2V
0.4V
0.8V
t XL
2.4V
(Note 1)
0.4V
AT Test Points
Note 1: The 2.4V and 0.4V levels are the voltages that the inputs are driven to during AC testing.
Note 2: The 2.2V and 0.8V levels are the voltages at which the timing tests are made.
2.2V
(Note 2)
0.8V
BAUDOUT Timing
N
XIN
t BHD
t BLD
t HW
BAUD OUT
(÷1)
BAUD OUT
(÷2)
BAUD OUT
(÷3)
BAUD OUT
(÷N.N > 3)
t BLD t BHD
t LW
t LW
t BLD
t
t HW
BHD
t HW
t BLD
t BHD
t LW
t HW = (N − 2)XIN CYCLES
t LW =2 XIN CTLES
5
5 Page 
GM16C550
Pin Descriptions
The following describes the function of all UART pins. Some
of these descriptions reference internal circuits.
In the following descriptions, a low represents a logic 0 (0V
nominal) and a high represents a logic 1 (+2.4V nominal).
INPUT SIGNALS
Chip Select (CS0, CS1, CS2 ) Pins 12-14: When CS0 and
CS1 are high and CS2 is low, the chip is selected. This
enable communication between the UART and the CPU. The
positive edge of an active Address Strobe signal latches the
decoded chip select signals, completing chip selection. If
ADS is always low, valid chip selects should stabilize
according to the CSW parameter.
Read (RD, RD ), Pins 22 and 21: When Rd is high or RD is
low while the chip selected, the CPR can read status information
or data from the selected UART register.
Note: Only an active RD or RD input is required to transfer
data from the UART during a read operation. Therefore
tie either the RD input permanently low or the RD input
permanently high, when it is not used.
Write (WR, WR ), Pin 19 and 18: When WR is high or
WR is low while the chip selected, the CPU can write
control words or data into the selected UART register.
Note: Only an active WR or WR input is required to transfer
data to the UART during a write operation. Therefore, tie
either the WR input permanently low or the WR input
permanently high, when it is not used.
Address Strobe ( ADS ), Pin 25: The positive edge of an
active Address Strobe ( ADS ) signal latches the Register
Select (A0, A1, A2) and Chip Select (CS0, CS1, CS2) signals.
Note: An active ADS input is required when the Register
Select (A0, A1, A2) signals are not stable for the
duration of a read or a write operation. If not required, tie
the ADS input permanently low.
Register Select (A0, A1, A2), Pins 26-28: Address signals
connected to these 3 inputs select a UART register for the CPU
to read from or write to during data transfer. A table of
registers and addresses is shown below. Note that the state of
the Divisor Latch Access Bit (DLAB), which is the most
significant bit of the Line Control Register, affects the
selection of certain UART registers. The DLAB must be set
high by the system software to access the Baud Generator
Divisor Latches.
Master Reset (MR), Pin 35: When this input is high it clears
all the registers (except the Receiver Buffer, Transmitter
Holding, and Divisor Latches), and the control logic of the
UART. The state of various output signals (SOUT, INTR,
OUT1 , OUT2 , RTS , DTR) are affected by an active MR
input (Refer to Table 1). This input is buffered with a TTL-
compatible Schmitt Trigger with 0.5V typical hysteresis.
Receiver Clock (RCLK), Pin 9: This input is the 16 X baud
rate clock for the receiver section of the chip.
Ring Indicator ( RI ), Pin 39: When low, this indicates
that a telephone ringing signal is received by the MODEM
or data set. The RI signal is a MODEM status input
Register Address
DLAB A2 A1 A0
Register
0 0 0 0 Receiver Buffer (read)
Transmitter Holding
Register (Write)
0 0 0 1 Interrupt Enable
× 0 1 0 Interrupt Identification (read)
× 0 1 0 FIFO Control (Write)
× 0 1 1 Line Control
× 1 0 0 MODEM Control
× 1 0 1 Line Status
× 1 1 0 MODEM Status
× 1 1 1 Scratch
1 0 0 0 Divisor Latch
0 (least significant byte)
1 0 0 1 Divisor Latch
(most significant byte)
Serial Input (SIN), Pin 10: Serial data input from the
communications link (peripheral device, MODEM, or data set).
Clear to Send ( CTS ), Pin 36: When low, this indicates that
the MODEM or data set is ready to exchange data. The CTS
signal is a MODEM status input whose conditions can be
tested by the CPU reading bit 4 (CTS) of the MODEM Status
Register. Bit 4 is the complement of the CTS signal. Bit 0
(DCTS) of the MODEM Status Register indicates whether the
CTS input has changed state since the previous reading of
the MODEM Status Register. CTS has no effect on the
Transmitter.
Note: Whenever the CTS bit of the MODEM Status Register
changes state, an interrupt is generated if the
MODEM Status Interrupt is enabled.
Data Set Ready ( DSR ), Pin 37: When low, this indicates that
the MODEM or data set is ready to establish the
communications link with the UART. The DSR signal is a
MODEM status input whose condition can be tested by the CPU
reading bit 5 (DSR) of the MODEM Status Register. Bit 5 is the
complement of the DSR signal. Bit 1 (DDSR) of the
MODEM Status Register indicates whether the DSR input
has changed state since the previous reading of the MODEM
Status Register.
Note: Whenever the DSR bit of the MODEM Status Register
changes state, an interrupt is generated if the
MODEM Status interrupt is enabled.
Data Carrier Detect ( DCD ), Pin 38: When low, indicates
that the data carrier has been detected by the MODEM or data
set. The DCD signal is a MODEM status input whose
condition can be tested by the Register. Bit 7 is the
complement of the DCD signal. Bit 3 (DDCD) of the
MODEM Status Register indicates whether the DCD input
has changed state since the previous reading of the MODEM
Status Register. DCD has no effect on the receiver.
Note: Whenever the DCD bit of the MODEM Status Register
changes state, an interrupt is generated if the
MODEM Status Interrupt is enabled.
whose condition can be tested by the CPU reading bit 6
( RI ) of the MODEM Status Register. Bit 6is the
complement of the RI signal. Bit 2 (TERI) of the MODEM
11
11 Page | ||
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