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GM71C18163C PDF даташит

Спецификация GM71C18163C изготовлена ​​​​«Hynix Semiconductor» и имеет функцию, называемую «1/048/576 WORDS x 16 BIT CMOS DYNAMIC RAM».

Детали детали

Номер произв GM71C18163C
Описание 1/048/576 WORDS x 16 BIT CMOS DYNAMIC RAM
Производители Hynix Semiconductor
логотип Hynix Semiconductor логотип 

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GM71C18163C Даташит, Описание, Даташиты
GM71C18163C
GM71CS18163CL
1,048,576 WORDS x 16 BIT
CMOS DYNAMIC RAM
Description
The GM71C(S)18163C/CL is the new
generation dynamic RAM organized 1,048,576
x 16 bit. GM71C(S)18163C/CL has realized
higher density, higher performance and various
functions by utilizing advanced CMOS process
technology. The GM71C(S)18163C/CL offers
Extended Data out(EDO) Mode as a high speed
access mode. Multiplexed address inputs permit
the GM71C(S)18163C/CL to be packaged in
standard 400 mil 42pin plastic SOJ, and standard
400mil 44(50)pin plastic TSOP II. The package
size provides high system bit densities and is
compatible with widely available automated
testing and insertion equipment.
Pin Configuration
Features
* 1,048,576 Words x 16 Bit Organization
* Extended Data Out Mode Capability
* Single Power Supply (5V+/-10%)
* Fast Access Time & Cycle Time
(Unit: ns)
t t t tRAC CAC RC HPC
GM71C(S)18163C/CL-5
GM71C(S)18163C/CL-6
GM71C(S)18163C/CL-7
50 13 84
60 15 104
70 18 124
20
25
30
* Low Power
Active : 1045/935/825mW (MAX)
Standby : 11mW (CMOS level : MAX)
0.83mW (L-version : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 1024 Refresh Cycles/16ms
* 1024 Refresh Cycles/128ms (L-version)
* Self Refresh Operation (L-version)
* Battery Back Up Operation (L-version)
* 2 CAS byte Control
42 SOJ
VCC 1
I/O0 2
I/O1 3
I/O2 4
I/O3 5
VCC 6
I/O4 7
I/O5 8
I/O6 9
I/O7 10
NC 11
NC 12
WE 13
RAS 14
NC 15
NC 16
A0 17
A1 18
A2 19
A3 20
VCC 21
44(50) TSOP II
42 VSS
41 I/O15
40 I/O14
39 I/O13
38 I/O12
37 VSS
36 I/O11
35 I/O10
34 I/O9
33 I/O8
32 NC
31 LCAS
30 UCAS
29 OE
28 A9
27 A8
26 A7
25 A6
24 A5
23 A4
22 VSS
(Top View)
VCC 1
I/O0 2
I/O1 3
I/O2 4
I/O3 5
VCC 6
I/O4 7
I/O5 8
I/O6 9
I/O7 10
NC 11
NC 15
NC 16
WE 17
RAS 18
A11 19
A10 20
A0 21
A1 22
A2 23
A3 24
VCC 25
50 VSS
49 I/O15
48 I/O14
47 I/O13
46 I/O12
45 VSS
44 I/O11
43 I/O10
42 I/O9
41 I/O8
40 NC
36 NC
35 LCAS
34 UCAS
33 OE
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 VSS
Rev 0.1 / Apr’01









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GM71C18163C Даташит, Описание, Даташиты
Pin Description
Pin
A0-A9
A0-A9
I/O0-I/O15
RAS
UCAS, LCAS
Function
Address Inputs
Refresh Address Inputs
Data Input/Data Output
Row Address Strobe
Column Address Strobe
GM71C18163C
GM71CS18163CL
Pin Function
WE Read/Write Enable
OE Output Enable
VCC Power (+5V)
VSS Ground
NC No Connection
Ordering Information
Type No.
GM71C(S)18163CJ/CLJ -5
GM71C(S)18163CJ/CLJ -6
GM71C(S)18163CJ/CLJ -7
GM71C(S)18163CT/CLT -5
GM71C(S)18163CT/CLT -6
GM71C(S)18163CT/CLT -7
Access Time
50ns
60ns
70ns
50ns
60ns
70ns
Package
400 Mil
42 Pin
Plastic SOJ
400 Mil
44(50) Pin
Plastic TSOP II
Absolute Maximum Ratings*
Symbol
Parameter
Rating
TA Ambient Temperature under Bias
0 ~ +70
TSTG
Storage Temperature
-55 ~ +125
VIN/OUT
Voltage on any Pin Relative to VSS
-1.0 ~ +7.0V
VCC Supply voltage Relative to VSS
IOUT Short Circuit Output Current
-1.0 ~ +7.0V
50
PD Power Dissipation
1.0
Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.
Unit
C
C
V
V
mA
W
Rev 0.1 / Apr’01









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GM71C18163C Даташит, Описание, Даташиты
GM71C18163C
GM71CS18163CL
Recommended DC Operating Conditions (TA = 0 ~ +70C)
Symbol
Parameter
Min Typ Max Unit
VCC Supply Voltage
4.5 5.0 5.5
V
VIH Input High Voltage
2.4 - 6.0 V
VIL Input Low Voltage
-1.0 -
0.8 V
Note: All voltage referred to Vss.
The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be
on the same level.
Truth Table
RAS LCAS UCAS WE OE Output
Operation
Notes
H D D D D Open
Standby
1,3
L
LH HL
Valid
Lower byte
L
HL HL
Valid
Upper byte
Read cycle
1,3
L L L H L Valid Word
L
LH LD
Open
Lower byte
L
L
L
L
L
L
L
L
H to L
H to L
H to L
H
L
L
H
L
L
H
L
H
L
L
L LD
Open
Upper byte Early write cycle 1,2,3
L L D Open
Word
H L H Undefined Lower byte
L
L
H
Undefined Upper byte
Delayed Write 1,2,3
cycle
L L H Undefined Word
H H to L L to H
L H to L L to H
L H to L L to H
Valid
Valid
Valid
Lower byte
Upper byte
Word
Read-modify
-write cycle
1,3
L DD
H DD
L DD
Open
Open
Open
Word
Word
Word
CBR Refresh
or
Self Refresh
(L-series)
1,3
L H H D D Open
L L L H H Open
Word
RAS-only
Refresh cycle
Read cycle
(Output disabled)
1,3
1,3
Notes: 1. H: High (inactive) L: Low(active) D: H or L
2. tWCS >= 0ns Early write cycle
tWCS <= 0ns Delayed write cycle
3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by earliest of
UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However
write OPERATION and output High-Z control are done independently by each UCAS,LCAS.
ex) if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.
Rev 0.1 / Apr’01










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