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GM82C765B PDF даташит

Спецификация GM82C765B изготовлена ​​​​«Hynix Semiconductor» и имеет функцию, называемую «FLOPPY DISK SUBSYSTEM CONTROLLER».

Детали детали

Номер произв GM82C765B
Описание FLOPPY DISK SUBSYSTEM CONTROLLER
Производители Hynix Semiconductor
логотип Hynix Semiconductor логотип 

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GM82C765B Даташит, Описание, Даташиты
GM82C765B
GM82C765B
FLOPPY DISK SUBSYSTEM CONTROLLER
General Description
The GM82C765B is a CMOS LSI device which interfaces a host
microprocessor to the floppy disk drive. It integrates the function of the
Formatter/Controller, Data Separator. Write Precompensation, Data rate
selection, Clock Generation, High Current Output Drivers, and TTL
compatible Schmitt Trigger Receivers. The GM82C765B consists of a
microprocessor interface, a microsequencer and a disk drive interface.
The host microprocessor interface of the GM82C765B supports a
12MHz, 286 microprocessor bus without the use of wait states. All inputs
within host microprocessor are Schmitt triggers, except for the data bus,
XTAL, and the host output sink 12mA.
Output drive capability is 20 LSTTL load, allowing direct
interconnection to bus structures without the use of buffers or transceivers.
On the disk drive interface, the GM82C765B includes data seperation that
has been designed to address high performance error rate on floppy disk
drives, and contains all the necessary logic to achieve classical 2nd order,
type2, phase locked loop performance. Write precompensation is included,
in addition to the usual formatting, encoding, decoding, step motor control,
and status sensing functions For PC/XT and PC/AT applications, the
device provides qualification of interrupt and DMA requests.
The disk drive interface of the GM82C765B connects directly to up to
four drives. All drive-related inputs are Schmitt triggers and the drive
outputs are open drain, and sink 48 mA.
The GM82C765B uses two clock inputs which provide the necessary
signals for internal timing. A 16MHz oscillator controls the data rate of
500, 250 and 125Kbits/sec, while a 9.6MHz oscillator controls the
300Kbit/sec data rate used in PC/AT designs.
The two XTAL oscillator circuits may be used for the 44-pin PLCC
package, while TTL clock inputs must be provided when using the 40-pin
DIP package.
In the PLCC version of the GM82C765B pins 17 and 40, which were
not utilized in DIP version of the GM82C765B, became DCHGEN (Disk
Change Enable) and DCHG (Disk Change) respectively. Both are active
LOW. DCHGEN is offered as an option for those designs that used the
original GM82C765B part where DCHG did not exist as direct into the
chip.
The GM82C765B has eight internal Registers. The 8 bit main status
register contains status information of the GM82C765B and may be
accessed any time. Another four status register under system control also
give various status and error information. The Control Register provides
support logic that latches the two LSBs used to select the desired data rate
that controls internal clock generation. The Operations Register replaces
the standard latched port used in floppy subsystem.
Features
IBM PC compatible format
(single and double density)
– Floppy disk control and
operations on chip
– In PC AT mode, provides required
signal qualification DMA channel
– BIOS compatible and dual speed
Spindle Drive support
Integrates Formatter/Controller/Data
Separation, Write Precompensation,
Data rate Selection, Clock
Generation, and drive interface
Drivers and Receivers into one chip
Multisector and Multitrack transfer
capability.
Direct Floppy Disk Drive interface
with no buffers needed
– 48mA sink output drivers
– Schmitt trigger Line Receivers
Enhanced Host Interface:
– Supports 12MHz, 286 u-processor
– Capable of driving 20 LSTTL
Load
Address mark detection circuitary
internal to Floppy Disk Controller
On chip Clock Generation
Two TTL Clock Inputs for 40-DIP
Two XTAL oscillator circuits for
44-Quad, PLCC
User programmable Track Stepping
Rate and Head load/unload time
Drivers up to four Floppy or micro
Floppy Disk Drives
Data transfer DMA or non-DMA
mode
Parallel seek operations on up to
four Drives
Internal power up reset circuitry
READ/WRITE access compatible
register with 8 or 12MHz 286
microprocessor with 0 wait states.
DMA timing corrected.
LOW POWER CMOS, +5V SUPPLY
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GM82C765B Даташит, Описание, Даташиты
Pin Configuration
GM82C765B
RD
WR
CS
AO
DACK
TC
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DMA
IRQ
LDOR
LDCR
RST
RDD
1
2
3
4
5
6
7
8
9
10
GM82C765B
11
12
13
14
15
16
17
18
19
20
40 VCC
39 IDX
38 TROO
37 WP
36 RPM, RWC
35 HDL
34 MO2. DS4
33 MO1, DS3
32 DS2
DCHG
WP
31 VSS
TROO
30 DS1
IDX
29 STEP
28 DIRC
VCC
RD
WR
27 WD
CS
26 WE
A0
25 HS
CACK
24 PCVAL
TC
23 CLK1
22 DRV
21 CLK2
39 38 37 36 35 34 33 32 31 30 29
40
41
42
43
44
1 GM82C765B PL
2
3
4
5
6
28
27
26
25
24
23
22
21
20
19
18
7 8 9 10 11 12 13 14 15 16 17
HS
PCVAL
XT1
XT1
DRV
XT2
XT2
RDD
RST
LDCR
LDOR
DBO DB2 DB4 DB6 DMA DCHGEN
DB1 DB3 DB5 DB7 IRQ
1. Pin Descriptions
PIN NO
DIP PLCC
11
MNEMOMIC
RD
SIGNAL NAME
READ
2 2 WR
WRITE
3 3 CS
A0
44
CHIP SELECT
ADDRESS LINE
DACK
55
DMA
ACKNOWLEDGE
(condinued on next page)
I/O FUNCTION
I Control Signal for transfer of data or status onto the
ST data bus by the GM82C765B
I Control signal for latching data form the bus into the
GM82C765B buffer register.
ST Selected when 0 (Low) allowing RD or WR
operation from the host
I Address line selecting data (=1) or status (=0)
ST information
(A0 = Logic 0 during WR is illegal)
I Used by the DMA Controller to transfer data from
ST the GM82C765B onto the bus. Logical equivalent to
CS and A0=1. In special or PC AT mode, this
signal is qualified by DMAEN from the Operation
Register.
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GM82C765B Даташит, Описание, Даташиты
GM82C765B
PIN MENMO
DIP PLCC -MIC
SIGNAL
NAME
6 6 TC
TERMINAL
COUNT
7-14
7-14
DBO thru
DB7
DATA BUS 0
Thru
DATA BUS 7
15 15 DMA
DIRECT
MEMORY
ACCESS
16 16 IRQ
INTERRUPT
REQUEST
DISK
17 DCHGEN CHANGE
ENABLE
17 18 LDOR
LOAD
OPERATIONS
REGISTER
18 19 LDCR
LOAD
CINTROL
REGISTER
19 20 RST
RESET
20 21 RDD
22 XT2
23 XT2
READ DISK
DATA
XTAL2
XTAL2
21
CLK2
CLOCK2
(condinued on next page)
I/O FUNCTION
This signal indicates to GM82C765B that data transfer is
complete. If DMA operational mode is selected for
command execution, TC will be qualified by DACK , but
not in the programmed I/O execution. In PC AT or Special
I
ST
mode, qualification by DACK requires the Operations
mode, qualification by DACK requires the operations
resister signal DMAEN to be logically true. Note also that
in PC AT mode, TC will be qualified by DACK , whether in
DMA or non-DMA host operation. programmed I/O in PC
AT mode will cause an abnormal termination error at the
completion of a command.
I/O
BI
8-Bit bi-directional, tri-state, data bus.
D0 is the least significant bit (LSB).
D7 is the most significant bit (MSB)
DMA request for byte transfer of data.
O In Special or PC AT mode, this pin is tristated, enabled by
BI the DMAEN signal from the Operation Register. This pin is
driven in the Base mode.
Interrupt request indicating the completion of command
O
BI
execution or data transfer requests (in non DMA mode).
Normally driven in base mode. In special or PC AT mode,
this pin is tri-stated, enabled by the DMAEN signal from the
Operations Resister.
I
ST
This input must be at logic = 0 to enable DCHG input
status at pin 40 to be placed on DB7 during a RD = 0 of
LDCR = 0. Internal pull-up.
Address decode which enables the loading of the Operations
I Resister. Internally gated with WR creates the strobe
ST which latches the two LSBS from the data bus into the
Operation Resister.
Address decode which enables the loading of the Control
I Resister. Internally gated with WR creates the strobe
ST which latches the two LSRs from thedata bus into the
Control Resister.
I
ST
Reset controller, placing microsequencer in idle. Resets
device outputs. Puts in base mode, not PC AT or Special
mode.
I
ST
This is the raw serial bit stream from the disk drive. Each
falling edge of the pulses represents a flux transition of the
encoded data.
O XTAL oscillator drive output for 44 pin PLCC should be
N left floating if TTL inputs used at pin 23.
I XTAL oscillator input used for non-standard data rates. It
N may be driven with a TTL level signal
I
N
TTL level clock input used for non-standard data rates is
9.6MHz for 300 kbs, and can only be selected from the
Control Register. * XT2 (PIN23) of 44 pin-PLCC
3










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Номер в каталогеОписаниеПроизводители
GM82C765FLOPPY DISK SUBSYSTEM CONTROLLERHynix Semiconductor
Hynix Semiconductor
GM82C765BFLOPPY DISK SUBSYSTEM CONTROLLERHynix Semiconductor
Hynix Semiconductor

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