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GP1020IGGPKR PDF даташит

Спецификация GP1020IGGPKR изготовлена ​​​​«Zarlink Semiconductor Inc» и имеет функцию, называемую «SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS».

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Номер произв GP1020IGGPKR
Описание SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS
Производители Zarlink Semiconductor Inc
логотип Zarlink Semiconductor Inc логотип 

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GP1020IGGPKR Даташит, Описание, Даташиты
FEBRUARY 1994
DS3605-2.2
GP1020
SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT
FOR GPS OR GLONASS RECEIVERS
The GP1020 is a six-channel CMOS digital correlator which
has been designed to work with the GP1010 L1-channel down-
converter or other integrated circuits, and may be used to acquire
and track the GPS C/A code or the GLONASS signals.
For each of the six channels the GP1020 includes independ-
ent digital down-conversion to baseband, C/A code generation,
correlation, and accumulate-and-dump registers.
The GP1020 interfaces with a microprocessor via a 16-bit
data bus to control the acquisition and tracking processes using
the various registers on the chip.
FEATURES
s Six Fully Independent Correlation Channels
s Switchable to Receive GPS or GLONASS Codes
s Input Multiplexer for Multiple GPS Front-Ends – Allows
Antenna Diversity
s Input Multiplexer for GLONASS Multiple (Separate
Channels) Front-Ends
s Digital Interface Compatible with Most 16 or 32-Bit
Microprocessors
s Fully Compatible with GP1010 GPS Receiver Front-End
s Sideways Stackable to give Multiples of Six Channels
s 120-pin Plastic Quad Flatpack
s Power Dissipation Less Than 500mW
APPLICATIONS
s GPS or GLONASS Navigation Systems
s High Integrity Combined Receivers
s GPS Geodetic Receivers
s GPS Time Reference
ORDERING INFORMATION
The GP1020 is available in 120-pin Quad Flatpacks (Gullwing
formed leads) in both Commercial (0°C to 170°C) and Industrial
(240°C to 185°C) grades. The ordering codes below are for
standard screened devices.
ORDERING CODES
GP1020 CG GPKR Commercial - Plastic 120-pin QFP (GP120)
GP1020 IG GPKR Industrial - Plastic 120-pin QFP (GP120)
90
91
61
60
GP1020
120 31
1 30 GP120
Fig 1 Pin connections - top view
ABSOLUTE MAXIMUM RATINGS
These are not the operating conditions, but are the absolute
limits which if exceeded, even momentarily, may cause perma-
nent damage. To ensure sustained correct operation the device
should be used within the limits given under Electrical Character-
istics.
Supply voltage (VDD) from ground (VSS):
20·3V to16·0 V
Input voltage (any input pin):
VSS20·3V to VDD10·3 V
Output voltage (any output pin):
VSS20·3V to VDD10·3 V
Storage temperature:
255°C to 1125°C
RELATED PRODUCTS
Part
Description
DW9255 35·42MHz SAW Filter
GP1010 GPS Receiver Front-End
Datasheet
Reference
DS3861
DS3076









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GP1020IGGPKR Даташит, Описание, Даташиты
GP1020
TYPICAL GPS RECEIVER (Fig. 2)
All satellites use the same L1 frequency of 1575·42MHz, but different Gold codes, so a single front-end may be used. To
achieve better sky coverage it may be desirable to use more than one antenna, in which case separate front-ends will be needed.
GND
15V
MASTERRESET
NAVIGATION
SOLUTION
GP1010
&
FILTER
MULTIPLE ANTENNAS TO GIVE
WIDER SKY COVERAGE
MASTER CLK
SAMPLE CLK
SIGN
MAG
VSS MASTER/SLAVE VDD CS
SIGN 0
MAG 0
SIGN 1
MAG 1
GP1020
(MASTER)
TIC OUT INT OUT
DECODE
DATA BUS (16)
ADDR BUS (8)
CONTROL 3
OPTIONAL
SECOND
GP1010
&
FILTER
TIC IN INT IN
CS
SIGN 0
MAG 0
OPTIONAL SECOND
SIGN 1
GP1020
MAG 1
(SLAVE)
VDD MASTER/SLAVE VSS
DECODE
15V
GND
MASTERRESET
Fig. 2 GPS receiver simplified block diagram
TYPICAL GLONASS RECEIVER (Fig. 3)
Each satellite will use a different ‘L1’ carrier frequency, in the range 1602·5625 to 1615·500MHz, with 0·5625MHz spacing,
but all with the same 511-bit spreading code. The normal method for receiving these signals is to use several front-ends, perhaps
with the first LNA and mixer common, but certainly with different final local oscillators and mixers.
L-BAND
DOWN
CONVERTER
GLONASS FRONT-END
FILTERS, AMPLIFIERS
AND MIXERS
FREQUENCY
GENERATOR
CHANNEL
SELECTION
AND ADC
CHANNEL
SELECTION
AND ADC
CHANNEL
SELECTION
AND ADC
CHANNEL
SELECTION
AND ADC
CHANNEL
SELECTION
AND ADC
CHANNEL
SELECTION
AND ADC
GND
15V
VSS MASTER/SLAVE VDD
SAMPLE CLK SAMP CLK
SIGN
SIGN 0
MAG
MAG 0
SIGN
MAG
SIGN 1
MAG 1
CS
SIGN
MAG
SIGN
MAG
SIGN
MAG
SIGN 2
MAG 2 GP1020
SIGN 3
MAG 3
INT OUT
SIGN 4
MAG 4
SIGN
MAG
SIGN 5
MAG 5
MASTER
CLOCK
NAVIGATION
SOLUTION
MASTERRESET
DECODE
DATA BUS (16)
ADDR BUS (8)
CONTROL 3
OSCILLATOR
FREQUENCY
SELECTION
Fig. 3 GLONASS receiver simplified block diagram
2









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GP1020IGGPKR Даташит, Описание, Даташиты
PIN DESCRIPTIONS (See Application Notes, p. 41)
All VSS and all VDD pins must be used in order to ensure
reliable operation. Several pins, such as Satellite Inputs 2 to
9 Sign and Magnitudes are also used for device testing, but
only as a secondary function.
Pin
No.
Signal
name
Type
Description
1 A7
I Register Address, bit 7
2 A8
I Register Address, bit 8
3 MASTER/
I Master or slave mode select
SLAVE
4 TSCAN
I Scan Test mode select
5 TCKS
I Test Clock select
6 TDI1
I Serial Test Data Input
7 MASTER
I Master Reset (active low)
RESET
8 MOT/INTEL I Motorola (hi) or Intel (lo) bus select
9 CS
I Chip Select (active low) for bus
10 VSS
11 VDD
12 WEN
2 Ground
1 Positive supply
I Bus control - see note 1
13 RW
I Bus control - see note 1
14 TMS2
I Test Mode Select 2
15 TMS1
I Test Mode Select 1
16 TMAG
O Test PRN Pattern Magnitude o/p
17 TSIGN
O Test PRN Pattern Sign output
18 MAG2
I/O Satellite Input 2, Magnitude
19 100/219kHz O Programmable Interrupt Timer clock
20 VDD
21 VSS
22 INTOUT
1 Positive supply
2 Ground
O Interrupt out to microprocessor
23 SIGN2
I/O Satellite Input 2, Sign
24 MAG3
I/O Satellite Input 3, Magnitude
25 SIGN3
I/O Satellite Input 3, Sign
26 MAG4
I/O Satellite Input 4, Magnitude
27 SIGN4
I/O Satellite Input 4, Sign
28 MAG5
I/O Satellite Input 5, Magnitude
29 SIGN5
I/O Satellite Input 5, Sign
30 MAG6
I/O Satellite Input 6, Magnitude
31 SIGN6
I/O Satellite Input 6, Sign
32 MAG7
I/O Satellite Input 7, Magnitude
33 SIGN7
I/O Satellite Input 7, Sign
34 MAG8
I/O Satellite Input 8, Magnitude
35 SIGN8
I/O Satellite Input 8, Sign
36 MAG9
I/O Satellite Input 9, Magnitude
37 SIGN9
I/O Satellite Input 9, Sign
38 MAG1
I/O Satellite Input 1, Magnitude
39 SIGN1
I/O Satellite Input 1, Sign
40 VSS
41 VDD
42 MAG0
2 Ground
1 Positive supply
I Satellite Input 0, Magnitude
43 SIGN0
I Satellite Input 0, Sign
44 SAMPCLK
O Sampling clock to down-converter
45 VDD
1 Positive supply
46 MASTERCLK I 40MHz Master Clock
47 VSS
48 Bias
2 Ground
O Bias for MASTERCLK in 600mV
AC-coupled mode
49 VSS
50 VDD
51 VSS
52 CLKSEL
2 Ground
1 Positive supply
2 Ground
I Sets 100/219kHz to 100or 219kHz
53 PLLLOCKIN I PLLlockstatusfromdown-converter
54 BITECNTL O BITE control to down-converter
55 GLONASSBIT I I/P to monitor GLONASS front-end
56 SLAVECLK I/O 20MHz clock from Master to slave
57 INTIN
I Interrupt to slave to sync to Master
58 TCK1
I/O Test Clock 1
59 TCK2
I/O Test Clock 2
60 TCK3
I/O Test Clock 3
61 TCK4
I/O Test Clock 4
62 TCK5
I/O Test Clock 5
63 TCK6
I/O Test Clock 6
64 TCK7
I/O Test Clock 7
65 TCK8
I Test Clock 8
GP1020
Pin
No.
Signal
name
Type
Description
66 TICIN
I TIC input to slave
67 TICOUT
O TIC output from Master
68 D0
I/O Data Bus, bit 0
69 D1
I/O Data Bus, bit 1
70 VSS
71 VDD
72 D2
2 Ground
1 Positive supply
I/O Data Bus, bit 2
73 D3
I/O Data Bus, bit 3
74 TIME MARK O One pulse per second output
75 RTCINT
I Real time clock interrupt input
76 MARKFB1
I Timemark line driver feedback
77 MARKFB2
I Timemark line driver feedback
78 D4
I/O Data Bus, bit 4
79 D5
I/O Data Bus, bit 5
80 VDD
81 VSS
82 D6
1 Positive supply
2 Ground
I/O Data Bus, bit 6
83 D7
I/O Data Bus, bit 7
84 WPROG
I Bus timing mode - see note 2
85 NANDA
I Test Structure - see note 3
86 NANDB
I Test Structure - see note 3
87 TDO
O Boundary Scan output
88 TCK
I Boundary Scan clock
89 TRST
I Boundary Scan reset
90 NANDOP
O Test Structure - see note 3
91 TMS
I Boundary Scan control
92 TDI
I Boundary Scan input
93 MARKFB3
I Timemark line driver feedback
94 TDO7
O Serial Test Data Output 7
95 DISCOP
O On/Off control for LNA by GP1010
96 TDO6
O Serial Test Data Output 6
97 TDO5
O Serial Test Data Output 5
98 D8
I/O Data Bus, bit 8
99 D9
I/O Data Bus, bit 9
100 VSS
101 VDD
102 D10
2 Ground
1 Positive supply
I/O Data Bus, bit 10
103 D11
I/O Data Bus, bit 11
104 TDO4
O Serial Test Data Output 4
105 TDO3
O Serial Test Data Output 3
106 TDO2
O Serial Test Data Output 2
107 TDO1
O Serial Test Data Output 1
108 D12
I/O Data Bus, bit 12
109 D13
I/O Data Bus, bit 13
110 VDD
111 VSS
112 D14
1 Positive supply
2 Ground
I/O Data Bus, bit 14
113 D15
I/O Data Bus, bit 15
114 ALE
I Address Latch Enable,
bus control
115 A1
I Register Address, bit 1 (LSB)
116 A2
I Register Address, bit 2
117 A3
I Register Address, bit 3
118 A4
I Register Address, bit 4
119 A5
I Register Address, bit 5
120 A6
I Register Address, bit 6
NOTE 1. The functions of RW and WEN pins depend on whether the
GP1020 is in Motorola™ (MOT/INTEL = ‘1’) or Intel™ mode (MOT/INTEL
= ‘0’). In Motorola mode, WEN is an enable (active high) and RW is Read/
Write select (‘1’ = Read). In Intel mode RW is Read, active low, and WEN
is Write, also active low.
MOT/INTEL
1
1
0
0
Mode
Motorola
Motorola
Intel
Intel
WEN RW Function
1 0 Write
1 1 Read
1 0 Read
0 1 Write
NOTE 2. WPROG is used to modify the timing of bus operations; when it
is held HIGH the internal write signal is ORed with ALE to allow time for the
internal address lines to stabilise; when it is held LOW there is no delay
added to write. NOTE 3. NANDOP (pin 90) is the output of a spare gate with
inputs on NANDA (pin 85) and NANDB (pin 86).
3










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Номер в каталогеОписаниеПроизводители
GP1020IGGPKRSIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERSZarlink Semiconductor Inc
Zarlink Semiconductor Inc

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