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GS72116ATP-8 PDF даташит

Спецификация GS72116ATP-8 изготовлена ​​​​«ETC» и имеет функцию, называемую «128K x 16 2Mb Asynchronous SRAM».

Детали детали

Номер произв GS72116ATP-8
Описание 128K x 16 2Mb Asynchronous SRAM
Производители ETC
логотип ETC логотип 

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GS72116ATP-8 Даташит, Описание, Даташиты
GS72116ATP/J/T/U
SOJ, TSOP, FP-BGA, TQFP
128K x 16
Commercial Temp
Industrial Temp
2Mb Asynchronous SRAM
7, 8, 10, 12 ns
3.3 V VDD
Center VDD and VSS
Features
• Fast access time: 7, 8, 10, 12 ns
• CMOS low power operation: 145/125/100/85 mA at
minimum cycle time
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Byte control
• Fully static operation
• Industrial Temperature Option: 40° to 85°C
• Package line up
J: 400 mil, 44-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
T: 10 mm x 10 mm, 44-pin TQFP
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
Description
The GS72116A is a high speed CMOS Static RAM organized
as 131,072 words by 16 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a sin-
gle 3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS72116A is available in a 6 mm x 8 mm
Fine Pitch BGA package, a 10 mm x 10 mm TQFP package, as
well as in 400 mil SOJ and 400 mil TSOP Type-II packages.
SOJ 128K x 16-Pin Configuration
A4 1
A3 2
A2 3
A1 4
A0 5
Top view
CE 6
DQ1 7
DQ2 8
DQ3 9
DQ4 10
VDD 11
44-pin
VSS 12
DQ5 13
SOJ
DQ6 14
DQ7 15
DQ8 16
WE 17
A15 18
A14 19
A13 20
A12 21
A16 22
Package J
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
DQ16
DQ15
DQ14
DQ13
VSS
VDD
DQ12
DQ11
DQ10
DQ9
NC
A8
A9
A10
A11
NC
Pin Descriptions
Symbol
A0A16
DQ1DQ16
CE
LB
UB
WE
OE
VDD
VSS
NC
Description
Address input
Data input/output
Chip enable input
Lower byte enable input
(DQ1 to DQ8)
Upper byte enable input
(DQ9 to DQ16)
Write enable input
Output enable input
+3.3 V power supply
Ground
No connect
Rev: 1.04a 10/2002
1/18
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, Giga Semiconductor, Inc.









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GS72116ATP-8 Даташит, Описание, Даташиты
44-Pin TQFP 128K x 16-Pin Configuration
A16 A15 A14 A13 A12 A11 A10 A9 OE UB LB
CE
44 43 42 41 40 39 38 37 36 35 34
1 33
DQ16
DQ1 2
32 DQ15
DQ2 3
31 DQ14
DQ3 4
30 DQ13
DQ4 5
29 VSS
VDD 6
28 VDD
VSS 7
27 DQ12
DQ5 8
26 DQ11
DQ6 9
25 DQ10
DQ7 10
24 DQ9
DQ8 11
23 NC
12 13 14 15 16 17 18 19 20 21 22
WE A0 A1 A2 A3 A4 NC A5 A6 A7 A8
Package T
Fine Pitch BGA 128K x 16-Bump Configuration
123456
A LB OE A0 A1 A2 NC
B DQ16 UB A3 A4 CE DQ1
C DQ14 DQ15 A5 A6 DQ2 DQ3
D VSS DQ13 NC A7 DQ4 VDD
E VDD DQ12 NC A16 DQ5 VSS
F DQ11 DQ10 A8 A9 DQ7 DQ6
G DQ9 NC A10 A11 WE DQ8
H NC A12 A13 A14 A15 NC
6 mm x 8 mm, 0.75 mm Bump Pitch
Top View
Package U
GS72116ATP/J/T/U
Rev: 1.04a 10/2002
2/18
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, Giga Semiconductor, Inc.









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GS72116ATP-8 Даташит, Описание, Даташиты
Block Diagram
TSOP-II 128K x 16-Pin Configuration
A4 1
A3 2
A2 3
A1 4
Top view
A0 5
CE 6
DQ1 7
DQ2 8
DQ3 9
DQ4 10
VDD 11
44-pin
VSS
DQ5
12
13
TSOP II
DQ6 14
DQ7 15
DQ8 16
WE 17
A15 18
A14 19
A13 20
A12 21
A16 22
44 A5
43 A6
42 A7
41 OE
40 UB
39 LB
38 DQ16
37 DQ15
36 DQ14
35
34
33
32
31
DQ13
VSS
VDD
DQ12
DQ11
30 DQ10
29 DQ9
28 NC
27 A8
26 A9
25 A10
24 A11
23 NC
Package TP
A0 Row
Decoder
Address
Input
Buffer
A16
CE
WE
OE
Control
UB _____
LB _____
Memory Array
Column
Decoder
I/O Buffer
DQ1 DQ16
GS72116ATP/J/T/U
Rev: 1.04a 10/2002
3/18
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, Giga Semiconductor, Inc.










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