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NCV51200 PDF даташит

Спецификация NCV51200 изготовлена ​​​​«ON Semiconductor» и имеет функцию, называемую «3 Amp Termination Regulator».

Детали детали

Номер произв NCV51200
Описание 3 Amp Termination Regulator
Производители ON Semiconductor
логотип ON Semiconductor логотип 

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NCV51200 Даташит, Описание, Даташиты
NCP51200, NCV51200
3 Amp VTT Termination
Regulator DDR1, DDR2,
DDR3, LPDDR3, DDR4
The NCP51200 is a source/sink Double Data Rate (DDR)
termination regulator specifically designed for low input voltage and
low−noise systems where space is a key consideration.
The NCP51200 maintains a fast transient response and only requires
a minimum output capacitance of 20 mF. The NCP51200 supports a
remote sensing function and all power requirements for DDR VTT bus
termination. The NCP51200 can also be used in low−power chipsets
and graphics processor cores that require dynamically adjustable
output voltages.
The NCP51200 is available in the thermally−efficient DFN10
Exposed Pad package, and is rated both Green and Pb−free.
Features
For Automotive Applications
Input Voltage Rails: Supports 2.5 V, 3.3 V and 5 V Rails
PVCC Voltage Range: 1.1 to 3.5 V
Integrated Power MOSFETs
Fast Load−Transient Response
PGOOD − Logic output pin to Monitor VTT Regulation
EN − Logic input pin for Shutdown mode
VRI − Reference Input Allows for Flexible Input Tracking Either
Directly or Through Resistor Divider
Remote Sensing (VTTS)
Built−in Soft Start, Under Voltage Lockout and Over Current Limit
Thermal Shutdown
Small, Low−Profile 10−pin, 3x3 DFN Package
NCV51200MWTXG − Wettable Flank Option for Enhanced Optical
Inspection
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable*
These Devices are Pb−Free and are RoHS Compliant
Applications
DDR Memory Termination
Desktop PC’s, Notebooks, and Workstations
Servers and Networking equipment
Telecom/Datacom, GSM Base Station
Graphics Processor Core Supplies
Set Top Boxes, LCD−TV/PDP−TV, Copier/Printers
Chipset/RAM Supplies as Low as 0.5 V
Active Bus Termination
www.onsemi.com
DFN10, 3x3, 0.5P
CASE 485C
MARKING DIAGRAM
51200
ALYWG
G
51200 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTION
VRI
PVCC
VTT
PGND
VTTS
+
1
2
3
4
5
GND
10 VCC
9 PGOOD
8 GND
7 EN
6 VRO
Exposed Pad
ORDERING INFORMATION
Device
NCP51200MNTXG
Package
DFN10
(Pb−Free)
Shipping
3000 / Tape &
Reel
NCV51200MNTXG* DFN10 3000 / Tape &
(Pb−Free)
Reel
NCV51200MWTXG* DFN10 3000 / Tape &
(Pb−Free)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
May, 2016 − Rev. 6
1
Publication Order Number:
NCP51200/D









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NCV51200 Даташит, Описание, Даташиты
NCP51200, NCV51200
PIN FUNCTION DESCRIPTION
Pin Number Pin Name
Pin Function
1 VRI VTT External Reference Input ( set to VDDQ / 2 thru resistor network ).
2
PVCC
Power input. Internally connected to the output source MOSFET.
3 VTT Power Output of the Linear Regulator.
4
PGND
Power Ground. Internally connected to the output sink MOSFET.
5
VTTS
VTT Sense Input. The VTTS pin provides accurate remote feedback sensing of VTT. Connect VTTS to the
remote DDR termination bypass capacitors.
6 VRO Independent Buffered VTT Reference Output. Sources and sinks over 5 mA. Connect to GND thru
0.1 mF ceramic capacitor.
7 EN Shutdown Control Input. CMOS compatible input. Logic high = enable, logic low = shutdown. Connect
to VDDQ for normal operation.
8
GND
Common Ground.
9
PGOOD
Power Good (Open Drain output).
10 VCC Analog power supply input. Connect to GND thru a 1 − 4.7 mF ceramic capacitor.
THERMAL Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple
PAD
vias for maximum power dissipation performance.
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC, PVCC, VTT, VTTS, VRI, VRO (Note 1)
−0.3 to 6.0
V
EN, PGOOD (Note 1)
−0.3 to 6.0
V
PGND to GND (Note 1)
−0.3 to +0.3
V
Storage Temperature
TSTG
−55 to 150
°C
Operating Junction Temperature Range
TJ 150 °C
ESD Capability, Human Body Model (Note 2)
ESDHBM
2000
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following method:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
DISSIPATION RATINGS
Package
10−Pin DFN
TA = 255C Power Rating
1.92 W
Derating Factor above
TA = 255C
19 mW/°C
TA = +855C Power Rating
0.79 W
RECOMMENED OPERATING CONDITIONS
Rating
Symbol
Value
Unit
Supply Voltage
VCC
2.375 to 5.5
V
Voltage Range
VRO
−0.1 to 1.8
V
VRI 0.5 to 1.8
PVCC, VTT, VTTS, EN, PGOOD
−0.1 to 3.5
PGND
−0.1 to +0.1
Operating Free−Air Temperature
TA
−40 to +125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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NCV51200 Даташит, Описание, Даташиты
NCP51200, NCV51200
ELECTRICAL CHARACTERISTICS
−40°C TA 125°C; VCC = 3.3 V; PVCC = 1.8 V; VRI = VTTS = 0.9 V; EN = VCC; COUT = 3 x 10 mF (Ceramic); unless otherwise noted.
Parameter
Conditions
Symbol Min Typ Max Units
Supply Current
VCC Supply Current
VCC Shutdown Current
VCC UVLO Threshold
TA = +25°C, EN = 3.3 V, No Load
TA = +25°C, EN = 0 V, VRI = 0 V, No Load
TA = +25°C, EN = 0 V, VRI > 0.4 V, No Load
Wake−up, TA = +25°C
Hysteresis
IVCC
IVCC SHD
VUVLO
2.15
0.7 1 mA
65 80 mA
200 400
2.3 2.375
V
50 mV
PVCC Supply Current
PVCC Shutdown Current
VTT Output
VTT Output Offset Voltage
VTT Voltage Tolerance to VRO
Source Current Limit
Sink Current Limit
Soft−start Current Limit
Timeout
TA = +25°C, EN = 3.3 V, No Load
TA = +25°C, EN = 0 V, No Load
VRO = 1.25 V (DDR1), ITT = 0 A
VRO = 0.9 V (DDR2), ITT = 0 A
PVCC = 1.5 V, VRO = 0.75 V (DDR3),
ITT = 0 A
−2 A ITT +2 A
VTTS = 90% * VRO
VTTS = 110% * VRO
IPVCC
IPVCC SHD
1 50 mA
0.1 50 mA
VOS −15
−15
−15
+15 mV
+15
+15
−25 +25 mV
3 4.5 A
3.5 5.5 A
TSS 200 ms
Discharge MOSFET
On−resistance
VRI = 0 V, VTT = 0.3 V, EN = 0 V, TA = +25°C
RDIS
18 25
W
VRI − Input Reference
VRI Voltage Range
VRI Input−bias Current
VRI UVLO Voltage
EN = 3.3 V
VRI rising
Hysteresis
VRO − Output Reference
VRO Voltage
VRO Voltage Tolerance to VRI
IRO = ±10 mA, 0.6 V VRI 1.25 V
VRO Source Current Limit
VRO = 0 V
VRO Sink Current Limit
VRO = 0 V
PGOOD − Powergood Comparator
PGOOD Lower Threshold
(with respect to VRO)
VRI
IRI
VRI UVLO
VRI HYS
0.5
360
1.8
+1
390 435
60
V
mA
mV
VRI V
−15 +15 mV
10 40
mA
10 40
mA
−23.5% −20% −17.5
%
V/V
PGOOD Upper Threshold
PGOOD Hysteresis
PGOOD Start−up Delay
PGOOD Leakage Current
PGOOD = False Delay
PGOOD Output Low Voltage
(with respect to VRO)
Start−up rising edge, VTTS within 15% of
VRO
VTTS = VRI (PGOOD = True)
PGOOD = VCC + 0.2 V
VTTS is beyond ±20% PGOOD trip thresholds
IGOOD = 4 mA
17.5%
20%
5%
2
23.5%
ms
1 mA
10 ms
0.4 V
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