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PDF 74LS76A Data sheet ( Hoja de datos )
| Número de pieza | 74LS76A | |
| Descripción | DUAL JK FLIP-FLOP | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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DUAL JK FLIP-FLOP
WITH SET AND CLEAR
The SN54 / 74LS76A offers individual J, K, Clock Pulse, Direct Set and Di-
rect Clear inputs. These dual flip-flops are designed so that when the clock
goes HIGH, the inputs are enabled and data will be accepted. The Logic Level
of the J and K inputs will perform according to the Truth Table as long as mini-
mum set-up times are observed. Input data is transferred to the outputs on the
HIGH-to-LOW clock transitions.
SN54/74LS76A
DUAL JK FLIP-FLOP
WITH SET AND CLEAR
LOW POWER SCHOTTKY
MODE SELECT — TRUTH TABLE
INPUTS
OUTPUTS
OPERATING MODE
SD CD
J
K
Q
Q
Set
Reset (Clear)
*Undetermined
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
LHXXHL
HLXXLH
L L XXHH
HHh h q q
HH l h LH
HHh l HL
HH
l
l
qq
*Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable
if SD and CD go HIGH simultaneously.
H,h = HIGH Voltage Level
L,l = LOW Voltage Level
X = Immaterial
l, h (q) = Lower case letters indicate the state of the referenced input (or output) one setup time prior
to the HIGH-to-LOW clock transition
Q
CLEAR (CD)
J
LOGIC DIAGRAM
CLOCK (CP)
Q
SET (SD)
K
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
27
16 K SD Q 15 12 K SD Q 11
1 CP
6 CP
4 J CD Q 14 9 J CD Q 10
3
VCC = PIN 5
GND = PIN 13
8
FAST AND LS TTL DATA
5-1
1 page | ||
| Páginas | Total 2 Páginas | |
| PDF Descargar | [ Datasheet 74LS76A.PDF ] | |
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