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PDF NSD-2101 Data sheet ( Hoja de datos )
| Número de pieza | NSD-2101 | |
| Descripción | Piezo Motor Driver ASIC | |
| Fabricantes | austriamicrosystems AG | |
| Logotipo |  |
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Datasheet
NSD-2101
Piezo Motor Driver ASIC for SQL-RV Series
Reduced Voltage SQUIGGLE® RV and UTAF™ Motors
1 General Description
2 Key Features
In combination with the SQUIGGLE® RV or UTAF, the NSD-2101
provides the industry’s smallest piezo motor drive solution with direct
battery drive; no boost circuit required.
The NSD-2101 is a dedicated piezo motor driver ASIC capable of
driving a SQL-RV Series Reduced Voltage SQUIGGLE® RV motor
or UTAF motor from a single 2.3 to 5.5 VDC supply. The motor can
be controlled using a standard I²C interface.
The NSD-2101 uses proprietary control technology to dynamically
adjust motor drive frequency to maintain optimal motor performance
and minimal power consumption over wide temperature ranges and
operating conditions. A built-in oscillator eliminates the need for an
external master clock.
Industry’s smallest piezo motor drive solution with direct battery
drive
- Wide input supply voltage: 2.3 to 5.5 VDC
- 1.8 x 1.8 mm 16-ball WL-CSP or 4 x 4 mm 16-pin QFN
(minimum order quantities for QFN apply)
Low power consumption:
- Proprietary design optimizes power usage
- Hard power-down mode for lowest power consumption
- Idle mode via software for reduced power while preserving
frequency calibration
Proprietary frequency tracking controls maximizes motor
performance over a range of operating and environmental
conditions
Built-in oscillator; no external clock or oscillator required
I²C interface for direct serial interface to microprocessor
On-chip registers for storing driver instructions
3 Applications
Figure 1. NSD-2101 Functional Block Diagram
The NSD-2101 is ideal for SQL-RV-1.8 SQUIGGLE® RV
piezoelectric motor driver and UTAF piezoelectric motor driver.
VCC
C1
XPD
SDA
SCL
ADR
C2
VDD
LDO
Power Save
BandGap
V/I-
References
Startup
Frequency
Tracking &
Control
VCO
PPTRIM
I²C Interface &
Registers
Control
VDDP
1 x MLA
Squiggle
Motor Driver
2.3V - 5.5V
+
-
Connection to
SQUIGGLE® RV
Motor
P1-1
P1-2
P2-1
P2-2
Connection to
UTAF motor
P1-1
P1-2
P2-1
P2-2
Test
VSS TM VSSP
www.austriamicrosystems.com/NSD-2101
Revision 0.6
1 - 22
1 page  
NSD-2101
Datasheet - Electrical Characteristics
6 Electrical Characteristics
Table 3. Operating Conditions
Symbol
Parameter
Conditions
VVDD
Voltage at VDD
Supply voltage
(VDD/VDDP rise time is between 10µs and
10ms. Above 5.0V only half bridge mode
should be used)
VVDDP
Voltage at VDDP
Driver supply
(VDD/VDDP rise time is between 10µs and
10ms. Above 5.0V only half bridge mode
should be used)
VVCC
VVSSP
VVSS
VLV
Tjunc
Ptot
Voltage at VCC
Voltage at VSSP
Voltage at VSS
Voltage at SDA,SCL, XPD, TM
Junction temperature
Total power dissipation
Internal LV supply
GND reference for drivers
GND reference
Total power dissipation needs to be less
than 1W to keep junction temperature in
specified range
IPd Power-down current consumption
XPD=LOW, temp=27ºC;
No activity on I²C
ISb Stand-by current consumption XPD=HIGH, pulse generation is stopped
INom Operating current consumption
Without output switching current
XPD=HIGH, temp=27ºC, VCO powered
IIdle Idle mode current consumption down, no digital activity; mode set by I²C,
frequency trimming preserved
Min
2.3
2.3
1.9
-0.1
0
-0.3
-30
Typ
6.1 DC/AC Characteristics for Digital Inputs and Outputs
Table 4. CMOS Input: XPD, ADR, CLK
Symbol
Parameter
Conditions
VIH
VIL
ILEAK
CIN
High level input voltage
Low level input voltage
Input leakage current
Capacitive Load
Min Typ
1.2
VSS
-1
Table 5. CMOS I²C Interface: SDA, SCL
Symbol
Parameter
VIH
VIL
ILEAK
High level input voltage
Low level input voltage
Input leakage current
VOH High level output voltage
VOL Low level output voltage
CL Capacitive load: SDA, SCL
RPU External pull-up resistor: SDA, SCL
SCL I²C write frequency
Conditions
Depending on external pull-up
resistor
At 3mA output current
Min
1.2
VSS
-1
VVDD -0.5
Typ
As defined by I²C spec
Maximum clock frequency to write
data
1.2
6.0
Max Units
5.5 V
5.5 V
3.0 V
0.1 V
0V
5.5 V
125 ºC
1W
5 µA
3.5 mA
10 mA
1.0 mA
Max Units
VDD V
0.3 V
+1 µA
15 pF
Max
VDD
0.3
+1
VVDD
VSS+0.4
50
7.1
400
Units
V
V
µA
V
V
pF
k
kHz
www.austriamicrosystems.com/NSD-2101
Revision 0.6
5 - 22
5 Page 
NSD-2101
Datasheet - Detailed Description
7.6 Control Register
The control register is used to trigger frequency calibration as well as to select and enable the drive phases.
Table 9. Control Register
Control Flag Mask
Abbr
Default
Description
1000 0000
0100 0000
0010 0000
PS[1]
PS[0]
0 Reserved (leave 0)
1 Phase Select for sensing: PS[1] PS[0]:
00=None
01=Phase1
1 10=Phase2
11= Both Phases
0001 0000
0 Reserved (leave 0)
0000 1000
0000 0100
CN[1]
CN[0]
0 Calibrate Now: CN[1] CN[0]:
00=None
01=Incremental
0 10=Sweep
11=reserved
0000 0010
P1
1 Enable Phase1
0000 0001
P2
1 Enable Phase2
7.7 Period Counter
The period counter is used to define the switching frequency of the motor. The pulse period is generated by dividing the internal VCO clock
frequency by the given period counter value. The MSB in the high byte of the pulse counter (p) is used as the MSB for the period counter.
At 25MHz clock a decimal period counter value of 125 gives an output frequency of 200 kHz. A period counter value of 126 results in a switching
frequency of 198.41 kHz. This is equal to a maximum frequency step of 1.59 kHz. The frequency resolution gets better for lower switching
frequencies assuming a fixed VCO clock frequency.
Table 10 lists out few examples to define period counter and output switching frequency relationship. The values are given for 25MHz typical
VCO clock frequency. The switch frequency is given as:
fD = 25MHz / period counter value
(EQ 1)
Table 10. Period Counter Values
Period Counter Value
Typ
Unit
0 0111 1101
200.00
kHz
0 0111 1110
198.41
kHz
0 1001 0001
172.4
kHz
0 1010 0110
150.60
kHz
0 1010 0111
149.70
kHz
1 1111 0011
50.10
kHz
1 1111 0100
50.00
kHz
www.austriamicrosystems.com/NSD-2101
Revision 0.6
11 - 22
11 Page | ||
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