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PDF NSD-1202 Data sheet ( Hoja de datos )
| Número de pieza | NSD-1202 | |
| Descripción | Dual Piezo Motor Driver IC | |
| Fabricantes | austriamicrosystems AG | |
| Logotipo |  |
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Data Sheet
NSD-1202
Dual Piezo Motor Driver IC for SQL Series
SQUIGGLE Motors
1 General Description
2 Key Features
The NSD-1202 is a dedicated piezo motor driver ASIC capable of
driving two SQL Series SQUIGGLE motors from a single 2.8 to 5.5
VDC supply.
The two motors can be controlled independently using a standard
I²C interface.
An on-chip DC-DC step-up converter generates the high supply
voltage (24 to 40 VDC) required by the piezoelectric elements of the
SQUIGGLE motor.
Four half bridge drivers create pairs of phase-shifted square waves
with ultrasonic frequency as required to drive SQL Series
SQUIGGLE motors.
Wide Input Supply Voltage Range: 2.8 to 5.5VDC
Step-up converter to generate programmable high-voltage
power supply (24 to 40V)
Minimum 65% efficiency (at VDD=2.8V, IOUT=25mA,
freq=2MHz)
4x output driver with defined rise/fall time
I²C interface
On chip registers store driver instructions
Power-down mode for minimal power consumption in stand-by
Small 4x4mm 16-Pin QFN Package
This part supersedes and is backward-compatible with the NSD-
1102.
3 Applications
Figure 1. NSD-1202 Functional Block Diagram
The NSD-1202 is ideal for SQUIGGLE piezoelectric motor driver.
VIN (2.8-5.5V)
L1
4.7µH
C1 22µF
VDD (2.8-5.5V)
LX
VDDH (programmable 24V...40V)
D1
VDDH
C2 1µF
XPD
Voltage
reference
Step-up
controller
TRIM
VSS
SDA
SCL
ADR
CLK
NSD-1202
I²C Interface
Registers
LOGIC
Level-
shifter
Level-
shifter
Level-
shifter
Level-
shifter
1
1
1
1
VSSP
DRV2P1
DRV2P2
DRV1P1
DRV1P2
www.austriamicrosystems.com/NSD-1202
Revision 0.2
1 - 13
1 page  
NSD-1202
Data Sheet - Electrical Characteristics
6.2 DC/AC Characteristics for Digital Inputs and Outputs
Table 5. CMOS Input: XPD, ADR, CLK
Symbol
Parameter
Conditions
VIH
VIL
ILEAK
CIN
High level input voltage
Low level input voltage
Input leakage current
Capacitive Load
Table 6. CMOS I²C Interface: SDA, SCL
Symbol
Parameter
VIH
VIL
ILEAK
High level input voltage
Low level input voltage
Input leakage current
VOH High level output voltage
VOL Low level output voltage
CL Capacitive load: SDA, SCL
RPU External pull-up resistor: SDA, SCL
SCL I²C write frequency
Conditions
Depending on external pull-up
resistor
@3mA output current
As defined by I²C spec
Maximum clock frequency to write
data
Min
1.2
VSS
Min
1.2
VSS
VVDD
-0.5
1.2
Typ Max Units
VDD V
0.3 V
1 µA
15 pF
Typ Max Units
VDD V
0.3 V
1 µA
VVDD
V
VSS+0.4
V
50 pF
6.0 7.1 kΩ
400 kHz
www.austriamicrosystems.com/NSD-1202
Revision 0.2
5 - 13
5 Page 
NSD-1202
Data Sheet - Package Drawings and Markings
9 Package Drawings and Markings
The devices are available in a 16LD QFN (4x4mm) package.
Figure 3. 16LD QFN (4x4mm) Package Drawings and Dimensions
56 7 8
49
3 10
2 11
#1 12
16 15 14 13
Symbol
A
A1
b
D
E
D2
E2
Min Nom Max
0.75 0.85 0.95
0.203 REF
0.25 0.30 0.35
4.00 BSC
4.00 BSC
2.30 2.40 2.50
2.30 2.40 2.50
Symbol
e
L
L1
P
aaa
ccc
Min Nom Max
0.65 BSC
0.40 0.50 0.60
0.10
45º BSC
0.15
0.10
Notes:
1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters, angle is in degrees.
3. Dimension b applies to metallized terminal and is measured between 0.25mm and 0.30mm from terminal tip. Dimension L1 represents
terminal full back from package edge up to 0.1mm is acceptable.
4. Coplanarity applies to the exposed heat slug as well as the terminal.
5. Radius on terminal is optional.
www.austriamicrosystems.com/NSD-1202
Revision 0.2
11 - 13
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