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PDF CLAB133UA01CG Data sheet ( Hoja de datos )

Número de pieza CLAB133UA01CG
Descripción Display Module
Fabricantes CHUNGHWA PICTURE TUBES 
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No Preview Available ! CLAB133UA01CG Hoja de datos, Descripción, Manual

Global LCD Panel Exchange Center
www.panelook.com
Chunghwa Picture Tubes, Ltd.
Technical Specification
To : ទڣ
Date : 2013/03/27
TFT LCD
CLAB133UA01 CG
ACCEPTED BY :
APPROVED BY
Herman Lee
CHECKED BY
Sean Lee
PREPARED BY
Product
Planning
Management General
Division
Prepared by : TFT-LCD Product Planning Management General Division.
CHUNGHWA PICTUER TUBES, LTD.
1127 Hopin Rd., Padeh City, Taoyuan, Taiwan 334, R.O.C.
TEL: +886-3-3675151 FAX: +886-3-377-3001
Doc.No: CLAB133UA01CG-ទڣ-Spec-Ver.1-20130327 Issue Date: 2013/03/27
U
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com

1 page




CLAB133UA01CG pdf
Global LCD Panel Exchange Center
CPT
www.panelook.com
CHUNGHWA PICTURES TUBES, LTD.,
(b)VCC-dip state
(1)when 3.0VЇVCCЊ2.7VΔtdЉ10 ms.
(2)when VCCІ2.7VΔVCC-dip condition should as the VCC-turn-off condition.
Vin=3.3V
td
*2) Typical value is Mosaic (32*36 Checker board) PatternΚ900 line mode.
Circuit conditionΚVCC=3.3 VΔfV=60 HzΔfH=55.92KHzΔfCLK=50.1MHz
!
Max value is Black PatternΚ900 line mode.
Circuit conditionΚVCC=3.3 VΔfV=60 Hz ΔfH=55.92KHzΔfCLK=50.1MHz
CPT Confidential
4/16
CLAB133UA01CG-ទڣ-Spec-Ver.1-20130327
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com

5 Page





CLAB133UA01CG arduino
Global LCD Panel Exchange Center
CPT
www.panelook.com
CHUNGHWA PICTURES TUBES, LTD.,
(2) Timing Chart
ITEM
SYNBOL
Frame Rate
-
DCLK
Frequency
Period
LCD
Timing
DENA
Horizontal total time
Horizontal Horizontal Active time
Horizontal Blank time
Vertical total time
Vertical Vertical Active time
Vertical Blank time
LVDS spread spectrum range *3)
fCLK
tCLK
tH
tHA
tHB
tV
tVA
tVB
MIN
55
44.82
18.02
880
800
80
926
900
26
-2
TYP
60
50.1
19.96
896
800
96
932
900
32
μNoteν
*1) DENA (DATA ENABLE) usually is positive.
*2) During the whole blank period, DCLK should keep input.
*3) LVDS input clock is 85MHz and modulation rate is fixed 100KHz
MAX
60
55.49
23.31
986
800
186
938
900
38
2
UNIT
Hz
MHz
ns
tCLK
tCLK
tCLK
tH
tH
tH
%
CPT Confidential
10/16
CLAB133UA01CG-ទڣ-Spec-Ver.1-20130327
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com

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