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PDF WM8521 Data sheet ( Hoja de datos )
| Número de pieza | WM8521 | |
| Descripción | Stereo DAC | |
| Fabricantes | Wolfson Microelectronics | |
| Logotipo |  |
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WM8521
Stereo DAC with Integrated Output Stage
for 2Vrms LINE OUT
DESCRIPTION
FEATURES
The WM8521 is a 192kHz stereo DAC with an integrated output
op-amp stage, designed to generate a 2.0Vrms output signal
directly, so reducing external component requirements in digital
audio applications.
WM8521 comes into two variants WM8521HC and WM8521H9
which offers different line drive output capabilities. WM8521HC
outputs 2Vrms at 12V supply, while WM8521H9 outputs
2.0Vrms at 9V supply. WM8521HC/H9 are designed for cost
sensitive consumer digital audio applications requiring 2Vrms
line output.
A 24-bit multi-bit sigma delta DAC is used with oversampling
digital interpolation filters. Digital audio input word lengths from
16-32 bits and sampling rates from 8kHz to 192kHz are
supported.
The audio interface supports I2S, Right Justified and DSP digital
audio formats.
Audio Performance
- DAC SNR 98dB (‘A’ weighted @ 48kHz)
- THD -81dB (‘A’ weighted @ 48kHz)
DAC Sampling Frequency: 8kHz – 192kHz
Pin Selectable Audio Data Interface Format
- I2S, 16-bit Right Justified or 16bit DSP
2.0 Vrms output at 12V or 9V supply
7.6V to 13.2V Analogue, 2.7V to 3.6 Digital Supply
14-lead SOIC Package
APPLICATIONS
Consumer digital audio applications requiring 2 Vrms output
- DVD Players
- Digital TV
- Digital Set Top Boxes
- A/V Receivers
The devices are controlled via a hardware interface which
provides access to features including de-emphasis, mute and
data formats. These devices are pin equivalent and are
available in a 14-lead SOIC package.
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
Production Data, February 2013, Rev 4.2
Copyright 2013 Wolfson Microelectronics plc
1 page  
Production Data
WM8521
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020 for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
Supplies are independent and can be applied in either order without damage to device.
CONDITION
Analogue Supply Voltage (AVDD)
Digital Supply voltage (DVDD)
Voltage range digital inputs
Master Clock Frequency
Operating temperature range, TA
Storage temperature prior to soldering
Storage temperature after soldering
MIN MAX
-0.3V
+15V
-0.3V
+4.2V
DGND -0.3V
DVDD +0.3V
50MHz
-25C
+85C
30C max / 85% RH max
-65C
+150C
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PD, Rev 4.2, February 2013
5
5 Page 
Production Data
WM8521
In I2S mode, the MSB is sampled on the second rising edge of BCLK following a LRCLK transition.
LRCLK is low during the left samples and high during the right samples.
LRCLK
LEFT CHANNEL
1/fs
RIGHT CHANNEL
BCLK
DIN
1 BCLK
123
MSB
n-2 n-1 n
LSB
1 BCLK
123
MSB
n-2 n-1 n
LSB
Figure 3 I2S Mode Timing Diagram
RIGHT JUSTIFIED MODE INPUT FORMAT
The WM8521 supports word lengths of up to 16-bits in right justified mode. If a word length shorter
than 16-bits is used, the unused bits should be padded with zeroes.
In right justified mode, LRCLK must be high for a minimum of 16 BCLKs and low for a minimum of 16
BCLKs. Any mark to space ratio on LRCLK is acceptable provided the above requirement is met.
The digital audio interface receives data on the DIN input. Audio Data is time multiplexed with LRCLK
indicating whether the left or right channel is present. LRCLK is also used as a timing reference to
indicate the beginning or end of the data words.
In right justified mode, the LSB is sampled on the rising edge of BCLK preceding a LRCLK transition.
LRCLK is high during the left samples and low during the right samples.
LRCLK
LEFT CHANNEL
1/fs
RIGHT CHANNEL
BCLK
DIN
123
14 15 16
123
14 15 16
MSB
LSB
MSB
LSB
Figure 4 Right Justified Mode Timing Diagram
DSP MODE INPUT FORMAT
A DSP compatible, time division multiplexed format is also supported by the WM8521.
This format is of the type where a ‘synch’ pulse is followed by two data words (left and right) of 16 bit
word length. The ‘synch’ pulse replaces the normal duration LRCLK, and DSP mode is auto-detected
by the shorter than normal duration of the LRCLK. If LRCLK is of 4 BCLK or less duration, the DSP
compatible format is selected. Mode A and Mode B formats are supported, selected by the state of
the FORMAT pin.
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PD, Rev 4.2, February 2013
11
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| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet WM8521.PDF ] | |
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