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82P31 PDF даташит

Спецификация 82P31 изготовлена ​​​​«Intel» и имеет функцию, называемую «Express Chipset».

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Номер произв 82P31
Описание Express Chipset
Производители Intel
логотип Intel логотип 

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82P31 Даташит, Описание, Даташиты
Intel® G31/P31 Express Chipset
Datasheet
— For the Intel® 82G31 Graphics and Memory Controller Hub
(GMCH) and the Intel® 82P31 Memory Controller Hub (MCH)
July 2007
Document Number: 317495-001









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82P31 Даташит, Описание, Даташиты
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY
WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL
PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY,
OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended
for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from
future changes to them.
The Intel® 82G31 GMCH and 82P31 MCH may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was
developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips
Electronics N.V. and North American Philips Corporation.
Intel, Pentium, Intel Core, Intel Inside, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2007, Intel Corporation. All rights reserved.
2 Datasheet









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82P31 Даташит, Описание, Даташиты
Contents
1 Introduction ...................................................................................................15
1.1 Terminology ........................................................................................18
1.2 Reference Documents ...........................................................................20
1.3 (G)MCH Overview.................................................................................21
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
1.3.8
1.3.9
Host Interface.........................................................................21
System Memory Interface.........................................................22
Direct Media Interface (DMI).....................................................23
PCI Express* Interface.............................................................23
Graphics Features (Intel® 82G31 GMCH Only) ............................. 24
SDVO and Analog Display Features (Intel® 82G31 GMCH Only) ...... 24
(G)MCH Clocking .....................................................................25
Power Management .................................................................26
Thermal Sensor ......................................................................26
2 Signal Description ...........................................................................................27
2.1 Host Interface Signals ...........................................................................28
2.2 System Memory (DDR2) Interface Signals................................................31
2.2.1
2.2.2
2.2.3
System Memory Channel A Interface Signals ...............................31
System Memory Channel B Interface Signals ...............................32
DDR2 DRAM Reference and Compensation Signals .......................33
2.3 PCI Express* Interface Signals ...............................................................33
2.4 Analog Display Signals (Intel® 82G31 GMCH Only) ....................................34
2.5 Clocks, Reset, and Miscellaneous ............................................................35
2.6 Direct Media Interface...........................................................................36
2.7 Serial DVO Interface (Intel® 82G31 GMCH Only) ....................................... 36
2.7.1 SDVO/PCI Express* Signal Mapping ...........................................38
2.8 Power and Ground ................................................................................39
3 System Address Map .......................................................................................41
3.1 Legacy Address Range ..........................................................................44
3.1.1 DOS Range (0h – 9_FFFFh).......................................................45
3.1.2 Legacy Video Area (A_0000h-B_FFFFh) ......................................45
3.1.3 Expansion Area (C_0000h-D_FFFFh) ..........................................46
3.1.4 Extended System BIOS Area (E_0000h-E_FFFFh).........................47
3.1.5 System BIOS Area (F_0000h-F_FFFFh).......................................47
3.1.6 PAM Memory Area Details.........................................................47
3.2 Main Memory Address Range (1MB – TOLUD) ...........................................48
3.2.1 ISA Hole (15 MB-16 MB) ..........................................................49
3.2.2 TSEG.....................................................................................49
3.2.3 Pre-allocated Memory ..............................................................49
3.3 PCI Memory Address Range (TOLUD – 4 GB) ............................................50
3.3.1 APIC Configuration Space (FEC0_0000h–FECF_FFFFh) ..................51
3.3.2 HSEG (FEDA_0000h–FEDB_FFFFh).............................................52
3.3.3 FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFF) ................. 52
3.3.4 High BIOS Area.......................................................................52
Datasheet
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