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CHY100 PDF даташит

Спецификация CHY100 изготовлена ​​​​«Power Integrations» и имеет функцию, называемую «Charger Interface Physical Layer IC».

Детали детали

Номер произв CHY100
Описание Charger Interface Physical Layer IC
Производители Power Integrations
логотип Power Integrations логотип 

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CHY100 Даташит, Описание, Даташиты
CHY100
ChiPhyFamily
Charger Interface Physical Layer IC
Product Highlights
Fully supports Quick Charge 2.0 specification
Class A: 5 V, 9 V, and 12 V output voltage
Class B: 5 V, 9 V, 12 V, and 20 V output voltage
USB battery charging specification revision 1.2 compatible
Automatic USB DCP shorting D+ to D- line
Default 5 V mode operation
Supports TOPSwitch and TinySwitch
Very low power consumption
Below 1 mW at 5 V output
Fail safe operation
Adjacent pin-to-pin short-circuit fault
Open circuit pin fault
Typical Applications
Battery chargers for smart phones, tablets, netbooks, digital
cameras, and bluetooth accessories
USB power output ports
Description
CHY100 is a low-cost USB high-voltage dedicated charging port
(HVDCP) interface IC for the Quick Charge 2.0 specification. It
incorporates all necessary functions to add Quick Charge 2.0
capability to Power Integrations’ switcher ICs such as TOPSwitch
or TinySwitch and other solutions employing traditional feedback
schemes.
CHY100 supports the full output voltage range of either Class A
or Class B. Optionally Class B can be inhibited for protecting the
battery charger from accidental damage.
CHY100 automatically detects whether a connected Powered
Device (PD) is Quick Charge 2.0 capable before enabling output
voltage adjustment. If a PD not compliant to Quick Charge 2.0 is
detected the CHY100 disables output voltage adjustment to
ensure safe operation with legacy 5 V only USB PDs.
VOUT
D+
D-
GND
Feedback
Network
BP
V3 D+
V2 CHY100 D-
U1
V1 R
GND
Figure 1. Typical Application Schematic.
PI-6988-071713
Figure 2. Package Option.
SO-8 (D Package)
www.powerint.com
This Product is Covered by Patents and/or Pending Patent Applications.
March 2014









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CHY100 Даташит, Описание, Даташиты
CHY100
BYPASS
(BP)
6V
3.9 V
+
BANDGAP
GND
OUTPUT
INHIBIT
+
2V
+
0.325 V
REFERENCE
(R)
D+
V3
V2 N3
V1 N2
N1
Figure 3. Functional Block Diagram.
CONTROL
LOGIC
(LOOKUP
TABLE)
S SET Q
R CLR Q
N5 D-
+
0.325 V
19.58 k
+
2V
GROUND
N4 (GND)
PI-7009-071513
Pin Functional Description
GROUND (GND) Pin
Ground.
V1 Pin
Open Drain input of output voltage adjustment switch.
Active for 9 V, 12 V, and 20 V output setting.
V2 Pin
Open Drain input of output voltage adjustment switch.
Active for 12 V, and 20 V output setting.
V3 Pin
Open Drain input of output voltage adjustment switch.
Active for 20 V output setting.
BYPASS (BP) Pin
Connection point for an external bypass capacitor for the
internally generated supply voltage.
REFERENCE (R) Pin
Connected to internal band-gap reference. Provides reference
current through connected resistor.
DATA LINE D+ Pin
USB D+ data line input.
DATA LINE D- Pin
USB D- data line input.
D Package (SO-8)
GND 1
V1 2
V2 3
V3 4
8 BP
7R
6 D+
5 D-
Figure 4. Pin Configuration.
PI-6987-071213
2
Rev. C 03/14
www.powerint.com









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CHY100 Даташит, Описание, Даташиты
CHY100
Functional Description
CHY100 is a low-cost USB high-voltage dedicated charging port
(HVDCP) interface IC for the Quick Charge 2.0 specification. It
incorporates all necessary functions to add Quick Charge 2.0
capability to Power Integrations’ integrated switcher ICs such as
TOPSwitch or TinySwitch.
CHY100 also supports other solutions with traditional feedback
schemes like optocoupler and secondary reference regulator
TL431 as depicted in Figure 5.
D1
C1 R6 R1
RBP
U3
RDAT_LKG
CBP
VOUT
D+
D-
GND
C6
U1
TL431
R5 V3
R4 V2
R3 V1
BP
CHY100
U2
D+
D-
R
R2
GND
RREF
PI-7008-071613
Figure 5. CHY100 with Traditional Output Regulation (CV Only).
Reference Input
Resister RREF at the REFERENCE pin is connected to an internal
band gap reference and provides an accurate reference current
for internal timing circuits. The recommended value is RREF = 127 k.
Quick Charge 2.0 Interface
At power-up CHY100 turns on switch N5 (see Figure 3) in 20 ms
or less after the BYPASS pin voltage has reached 4 V. Switch
N4 and output switches N1 to N3 remain off. This sets the
default 5 V output voltage level. With D+ and D- short-circuited
the normal handshake between the AC-DC adapter (DCP) and
powered devices (PD) as described in the USB Battery Charging
Specification 1.2 can commence. After switch N5 has been
turned on CHY100 starts monitoring the voltage level at D+. If it
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below
will enter
D+ drops
any time below 0.325 V CHY100 resets the 1.25 seconds timer
and stays in USB Battery Charging Specification 1.2 compatibility
mode with a default output voltage of 5 V.
Once CHY100 has entered Quick Charge 2.0 operation mode
switch N5 will be turned off. Additionally switch N4 is turned on
connecting a 19.53 kpull-down resistor to D-. As soon as the
voltage at D- has dropped low (<0.325 V) for at least 1 ms
CHY100 starts accepting requests for different AC-DC adapter
output voltages by means of applied voltage levels at data lines
D+ and D- through the powered device. Table 1 summarizes
the output voltage lookup table, corresponding AC-DC adapter
output voltages and status of switches N1 to N3.
CHY100 supports the full output voltage range of Quick Charge
2.0 Class A (5 V, 9 V, or 12 V) or Class B (5 V, 9 V, 12 V, or 20 V).
It automatically detects either Quick Charge 2.0 capable powered
devices (PD) or legacy PDs compliant with the USB Battery
Charging Specification revision 1.2 and only enables output
voltage adjustment accordingly.
Shunt Regulator
The internal shunt regulator clamps the BYPASS pin at 6 V
when current is provided through an external resistor (RBP in
Figure 5). This facilitates powering of CHY100 externally over
the wide power supply output voltage range of 5 V to 20 V.
Recommended values are RBP = 4.53 kand CBP = 220 nF.
BYPASS Pin Undervoltage
The BYPASS pin undervoltage circuitry resets the CHY100
when the BYPASS pin voltage drops below 3.9 V. Once the
BYPASS pin voltage drops below 3.9 V it must rise back to 4 V
to enable correct operation.
D+
0.6 V
3.3 V
3.3 V
0.6 V
D-
0.6 V
0.6 V
3.3 V
GND
Output
12 V
9V
20 V
5 V (default)
Switch Status
N1 = N2 = On, N3 = Off
N1 = On, N2 = N3 = Off
N1 = N2 = N3 = On
N1 = N2 = N3 = Off
Table 1. Output Voltage Lookup Table.
For Quick Charge 2.0 Class A support only, the V3 pin has to be
connected to the BYPASS pin (directly or through a resistor up to
100 k). This will inhibit any requests for setting a 20 V output.
At USB cable disconnect the voltage level at D+ is pulled down
by resistor RDAT(LKG) (see Figure 5). Once it drops below 0.325 V
CHY100 will turn on switch N5 (thereby short-circuiting D+ and
D-) and turns off switches N1 to N4. This sets the default output
voltage of 5 V. The recommended value for RDAT(LKG) = 390 k.
www.powerint.com
3
Rev. C 03/14










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