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PDF NL128102BC29-01C Data sheet ( Hoja de datos )
| Número de pieza | NL128102BC29-01C | |
| Descripción | TFT COLOR LCD MODULE | |
| Fabricantes | NEC | |
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TFT COLOR LCD MODULE
NL128102BC29-01B
NL128102BC29-01C
48.0 cm (19.0 Type)
SXGA
LVDS interface (2port)
DATA SHEET
DOD-PD-0744 (1st edition)
All information is subject to change without notice.
Please confirm the sales representative before
starting to design your system.
Document Number: DOD-PD-0744 (1st edition)
Published date: December 2004 CP(N)
1 ¤ NEC LCD Technologies, Ltd.
2004 All rights reserved.
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NL128102BC29-01B/01C
2. GENERAL SPECIFICATIONS
Display area
Diagonal size of display
Drive system
Display color
Pixel
Pixel arrangement
Dot pitch
Pixel pitch
Module size
Weight
Contrast ratio
Viewing angle
Designed viewing direction
Polarizer surface
Polarizer pencil-hardness
Color gamut
Response time
Luminance
White chromaticity
Signal system
Power supply voltage
Backlight
Power consumption
376.32 (H) u 301.056 (V) mm
48.0 cm (19.0 inches)
a-Si TFT active matrix
16,777,216 colors
1,280 (H) u 1,024 (V) pixels
RGB (Red dot, Green dot, Blue dot) vertical stripe
0.098 (H) u 0.294 (V) mm
0.294 (H) u 0.294 (V) mm
404.2 (W) u 330.0 (H) u 22.0 (D) mm (typ.)
2,900 g (typ.)
450:1 (typ.)
At the contrast ratio t10:1
x Horizontal: Right side 85q (typ.), Left side 85q (typ.)
x Vertical: Up side 85q (typ.), Down side 85q (typ.)
Viewing angle with optimum grayscale (J=2.2): normal axis
Antiglare
2H (min.) [by JIS K5400]
At LCD panel center
72 % (typ.) [against NTSC color space]
Ton+Toff (10%mo 90%)
20 ms (typ.)
NL128102BC29-01B
NL128102BC29-01C
At IBL=6.0mArms / lamp
280cd/m2 (typ.)
At IBL=6.0mArms / lamp
270cd/m2 (typ.)
NL128102BC29-01B
Wx, Wy = (0.313, 0.329) (typ.)
NL128102BC29-01C
Wx, Wy = (0.300, 0.315) (typ.)
LVDS 2 port
8bit digital signals for data of RGB colors, Dot clock (CLK),
Data enable (DE)
LCD panel signal processing board: 5.0V
Edge light type: 6 cold cathode fluorescent lamps (without inverter)
At IBL=6.0mArms / lamp and checkered flag pattern
26.8 W (typ., Power dissipation of the inverter is not included.)
DATA SHEET DOD-PD-0744 (1st edition)
5
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NL128102BC29-01B/01C
4.4 POWER SUPPLY VOLTAGE SEQUENCE
VDD
Note1
ON
4.5V
0V
0.1ms < Tr < 80ms
OFF
4.0V 4.5V
20ms max.
Toff > 200ms
Display signals*
TxSEL signal
Note2
0V
VALID period
10 < t < 35ms
10 < t < 35ms
* These signals should be measured at the terminal of 100: resistance.
Note1: In terms of voltage variation (voltage drop) while VDD rising edge is below 4.5V, a protection
circuit may work, and then this product may not work.
Note2: Display signals (DA0+/-, DA1+/-, DA2+/-, DA3+/-, CKA+/-, DB0+/-, DB1+/-, DB2+/-,
DB3+/-, CKB+/-) and TxSEL signal must be "0" voltage, exclude the VALID period (See
above sequence diagram). If these signals are higher than 0.3V, the internal circuit is damaged.
If some of display and function signals of this product are cut while this product is working,
even if the signal input to it once again, it might not work normally. If customer stops the
display and function signals, they should be cut VDD.
Note3: VDD should be 4.5V or more while VDD ON period.
Note4: The backlight power supply voltage should be inputted within the valid period of display and
function signals, in order to avoid unstable data display.
DATA SHEET DOD-PD-0744 (1st edition)
11
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| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet NL128102BC29-01C.PDF ] | |
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