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PDF NAND512R4A2D Data sheet ( Hoja de datos )
| Número de pieza | NAND512R4A2D | |
| Descripción | SLC NAND flash memories | |
| Fabricantes | Numonyx | |
| Logotipo |  |
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NAND512xxA2D
512-Mbit, 528-byte/264-word page,
1.8 V/3 V, SLC NAND flash memories
Features
High density SLC NAND flash memories
– 512 Mbit memory array
– Cost effective solutions for mass
storage applications
NAND interface
– x8 or x16 bus width
– Multiplexed address/data
Supply voltage: 1.8 V, 3 V
Page size
– x8 device: (512 + 16 spare) bytes
– x16 device: (256 + 8 spare) words
Block size
– x8 device: (16 K + 512 spare) bytes
– x16 device: (8 K + 256 spare) words
Page read/program
– Random access:
12 µs (3 V)/15 µs (1.8 V) (max)
– Sequential access:
30 ns (3 V)/50 ns (1.8 V) (min)
– Page program time: 200 µs (typ)
Copy back program mode
Fast block erase: 1.5 ms (typ)
Status register
Electronic signature
Chip Enable ‘don’t care’
Hardware data protection: program/erase
locked during power transitions
Security features
– OTP area
TSOP48 12 x 20 mm (N)
FBGA
VFBGA63 9 x 11 x 1.05 mm (ZA)
– Serial number (unique ID)
Data integrity
– 100,000 program/erase cycles (with
ECC)
– 10 years data retention
RoHS compliant packages
Development tools
– Error correction code models
– Bad blocks management and wear
leveling algorithms
– Hardware simulation models
Table 1.
Device summary
NAND512xxA2D
NAND512R3A2D
NAND512R4A2D
NAND512W3A2D
NAND512W4A2D
July 2010
210217 - Rev 9
1/52
www.numonyx.com
1
1 page  
NAND512xxA2D
List of figures
List of figures
Figure 1.
Figure 2.
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Figure 25.
Figure 26.
Figure 27.
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Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TSOP48 connections - x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VFBGA63 connections - x8 devices (top view through package) . . . . . . . . . . . . . . . . . . . . 10
Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pointer operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pointer operations for programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read (A,B,C) operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Sequential row read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Sequential row read block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Read block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Page program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Copy back operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Bad block management flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Equivalent testing circuit for AC characteristics measurement . . . . . . . . . . . . . . . . . . . . . . 34
Command Latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Address Latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Data Input Latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Sequential data output after read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Read status register AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Read electronic signature AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Page read A/ read B operation AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Read C operation, one page AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Page program AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Block erase AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Program/erase enable waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Program/erase disable waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Ready/Busy AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Ready/Busy load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Resistor value versus waveform timings for Ready/Busy signal. . . . . . . . . . . . . . . . . . . . . 46
Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline . . . . . . . . . . . . 47
VFBGA63 9 x 11 x 1.05 mm - 6 x 8 +15, 0.80 mm pitch, package outline . . . . . . . . . . . . . 48
5/52
5 Page 
NAND512xxA2D
2 Memory array organization
Memory array organization
The memory array is made up of NAND structures where 16 cells are connected in series.
The memory array is organized in blocks where each block contains 32 pages. The array is
split into two areas, the main area and the spare area. The main area of the array is used to
store data whereas the spare area is typically used to store error correction codes, software
flags or bad block identification.
In x8 devices the pages are split into a main area with two half pages of 256 bytes each and
a spare area of 16 bytes. In the x16 devices the pages are split into a 256-word main area
and an 8-word spare area. Refer to Figure 5: Memory array organization.
Bad blocks
The NAND flash 528-byte/264-word page devices may contain bad blocks, that is blocks
that contain one or more invalid bits whose reliability is not guaranteed. Additional bad
blocks may develop during the lifetime of the device.
The bad block information is written prior to shipping (refer to Section 7.1: Bad block
management for more details).
Table 4 shows the minimum number of valid blocks in each device. The values shown
include both the bad blocks that are present when the device is shipped and the bad blocks
that could develop later on.
These blocks need to be managed using bad blocks management, block replacement or
error correction codes (refer to Section 7: Software algorithms).
Table 4. Valid blocks
Density of device
512 Mbits
Min
4016
Max
4096
11/52
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| PDF Descargar | [ Datasheet NAND512R4A2D.PDF ] | |
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