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PDF 96NQ03LT Data sheet ( Hoja de datos )
| Número de pieza | 96NQ03LT | |
| Descripción | N-channel enhancement mode field-effect transistor | |
| Fabricantes | NXP Semiconductors | |
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PHP/PHB/PHD96NQ03LT
N-channel enhancement mode field-effect transistor
Rev. 03 — 23 October 2001
Product data
1. Description
N-channel logic level field-effect power transistor in a plastic package using
TrenchMOS™1 technology.
Product availability:
PHP96NQ03LT in SOT78 (TO-220AB)
PHB96NQ03LT in SOT404 (D2-PAK)
PHD96NQ03LT in SOT428 (D-PAK).
2. Features
s Low gate charge
s Low on-state resistance.
3. Applications
s Optimized as a control FET in DC to DC converters.
4. Pinning information
Table 1: Pinning - SOT78, SOT404, SOT428 simplified outline and symbol
Pin Description
Simplified outline
1 gate (g)
2 drain (d)
mb
[1]
mb
mb
3 source (s)
mb mounting base,
connected to drain (d)
MBK106
123
SOT78 (TO-220AB)
2
1 3 MBK116
SOT404 (D2-PAK)
2
1
Top view
3
MBK091
SOT428 (D-PAK)
Symbol
g
MBB076
d
s
[1] It is not possible to make connection to pin 2 of the SOT404 and SOT428 packages.
1. TrenchMOS is a trademark of Koninklijke Philips Electronics N.V.
1 page  
Philips Semiconductors
PHP/PHB/PHD96NQ03LT
N-channel enhancement mode field-effect transistor
8. Characteristics
Table 5: Characteristics
Tj = 25 °C unless otherwise specified
Symbol Parameter
Conditions
Static characteristics
V(BR)DSS drain-source breakdown voltage
VGS(th) gate-source threshold voltage
IDSS drain-source leakage current
IGSS
RDSon
gate-source leakage current
drain-source on-state resistance
Dynamic characteristics
ID = 0.25 mA; VGS = 0 V
Tj = 25 °C
Tj = −55 °C
ID = 1 mA; VDS = VGS; Figure 9
Tj = 25 °C
Tj = 175 °C
Tj = −55 °C
VDS = 25 V; VGS = 0 V
Tj = 25 °C
Tj = 175 °C
VGS = ±15 V; VDS = 0 V
VGS = 5 V; ID = 25 A; Figure 7 and 8
Tj = 25 °C
Tj = 175 °C
VGS = 10 V; ID = 25 A; Figure 7
Tj = 25 °C
Qg(tot) total gate charge
Qgs gate-source charge
Qgd gate-drain (Miller) charge
Ciss input capacitance
Coss output capacitance
Crss reverse transfer capacitance
td(on)
turn-on delay time
tr turn-on rise time
td(off)
turn-off delay time
tf turn-off fall time
Source-drain diode
ID = 50 A; VDD = 15 V; VGS = 5 V; Figure 13
VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 11
VDD = 15 V; ID = 12.5 A; VGS = 5 V;
RG = 5.6 Ω; resistive load
VSD source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 12
trr reverse recovery time
IS = 10 A; dIS/dt = −100 A/µs; VGS = 0 V
Qr recovered charge
Min Typ Max Unit
25 - V
22 - - V
1 1.5 2 V
0.5 - - V
- - 2.3 V
- 0.05 1 µA
- - 500 µA
- 10 100 nA
- 5.6 7.5 mΩ
- 10 13.5 mΩ
- 4.2 4.95 mΩ
- 26.7 - nC
- 8.5 - nC
- 8.4 - nC
- 2200 - pF
- 725 - pF
- 290 - pF
- 18 - ns
- 70 - ns
- 75 - ns
- 70 - ns
- 0.9 1.2 V
- 43 - ns
- 40 - nC
9397 750 08963
Product data
Rev. 03 — 23 October 2001
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
5 of 14
5 Page 
Philips Semiconductors
PHP/PHB/PHD96NQ03LT
N-channel enhancement mode field-effect transistor
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped)
SOT428
seating plane
y
A
EA
A2
b2 A1
mounting
base
D
HE
L2
2
1
L
3
b1
e
b wM A
e1
L1
c
E1
D1
0 10 20 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT max.
A1(1)
A2
b
b1
max.
b2
c
mm 2.38 0.65 0.89 0.89 1.1 5.36 0.4
2.22 0.45 0.71 0.71 0.9 5.26 0.2
D D1 E E1
max. max. max. min.
e
e1
HE
max.
L
6.22 4.81 6.73 4.0 2.285 4.57 10.4 2.95
5.98 4.45 6.47
9.6 2.55
L1
min.
0.5
L2
0.7
0.5
Note
1. Measured from heatsink back to lead.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
EIAJ
EUROPEAN
PROJECTION
SOT428
TO-252
SC-63
w
y
max.
0.2 0.2
ISSUE DATE
98-04-07
99-09-13
Fig 16. SOT428 (D-PAK).
9397 750 08963
Product data
Rev. 03 — 23 October 2001
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
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