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PDF NTP3000 Data sheet ( Hoja de datos )
| Número de pieza | NTP3000 | |
| Descripción | 2.1 CHANNEL FULL DIGITAL AMPLIFIER | |
| Fabricantes | NeoFidelity | |
| Logotipo |  |
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 1. 2.1 Ch, Full Digital Amplifier  Hay una vista previa y un enlace de descarga de NTP3000 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Power Integrated Processor for Digital Amplifier
NTP3000
NTP3000 1CHIP 2.1CHANNELFULLDIGITALAMPLIFIER
Features
Stereo (30W ⅹ 2)
2.1 channel (15Wⅹ2 + 30W)
Wide Supply Voltage Range
(7V~30V)
Floating Point Operation
18 Programmable Biquad Filters
Speaker Compensation
DC cut, LPF, HPF
Parametric Equalizer
PWM Output for External Subwoofer
3D Surround
7 Band Graphic Equalizer
100 dB Dynamic Range
Adaptive Loudness Compensator
based on Psycho Acoustics
Applications
Plasma TV, LCD TV
Docking Station
Mini-Component Audio
Description
NTP3000 is a single chip full digital audio
amplifier including power stage for stereo or
2.1 channel amplifier system. NTP3000 is
integrated with versatile digital audio signal
processing functions, high-fidelity fully digital
PWM modulator and two high-power full bridge
MOSFET stages.
NTP3000 receives 2-channel serial audio data
with sampling frequency from 8 kHz to 192
kHz. It delivers 2x30W in stereo mode or
2x15W + 1x30W in 2.1 channel mode without
heat sink.
Combining use of built-in mixer and biquad
filters can make additional preprocessing like
bass management, loudness control, loud-
speaker response compensation and preset
parametric equalizers possible.
All the functions of NTP3000 are set by I2C
register configuration.
Package
56 pin MLF 8mm by 8mm
BST1A
VDR1A
/RESET
AD
VSS_IO
CLK_I
CLK_O
VDD_IO
DGNDPLL
AGNDPLL
LFM
AVDDPLL
DVDDPLL
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NTP3000
42 NC
41 VDR2A
40 BST2A
39 PGND2A
38 PGND2A
37 OUT2A
36 OUT2A
35 PVDD2A
34 PVDD2A
33 PVDD2B
32 PVDD2B
31 OUT2B
30 OUT2B
29 PGND2B
Figure 1 NTP3000 Pin Assignment
NeoFidelity, Inc. #1009, Ace Twin Tower 2, 212-30, Guro-dong, Guro-gu, Seoul 152-766 Korea, Phone +82-2-6675-
Copyright © NeoFidelity, Inc. 2005 All rights Reserved. June, 2005
Disclaimer
NeoFidelity, Inc. reserves the right to make changes without notice in the product described in this datasheet
Copyright © NeoFidelity, Inc. 2005
1
Preliminary datasheet – NeoFidelity reserves the right to change specifications at any time without prior notice
R0.73-11.2006
1 page  
Power Integrated Processor for Digital Amplifier
NTP3000
Low threshold point
Input Leakage Current
Tri-State output
Leakage Current
Pull-up Resistor
Pull-down Resistor
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
OUT On Resistance
OUT Current Limit
Thermal Shutdown
Temperature
Il
Ioz
Rpu
Rpd
Vol
Voh
Iol
Ioh
Rdson
-
-
-
-
Iol=2,4,…24mA
Ioh=2,4,…24mA
Vol=0.4V, 4mA
Voh=2.4V, 4mA
PVDDXX=7.5V
Sourcing and Sinking
39k
40k
2.4
4.7
5.6
65k
56k
8.0
11.9
0.1
8
160
±10
±10
116k
108k
0.4
10
19
uA
uA
Ω
Ω
V
V
mA
mA
Ω
A
°C
3.4. Performance Specification
Parameter
SNR
THD+N
Output Power
Output Power
Condition
AES17, A-weighting filter
1W, 1kHz
Unclip
Unclip
Min Typ Max Unit
100 dB
0.01 %
2x30
W
2x15+30
W
3.5. Switching Characteristics – I2C Control Port
Parameter
SCL Clock Frequency
Hold time for START Condition
Low period of the SCL clock
High period of the SCL clock
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Setup time for STOP Condition
Symbol
fscl
Thdsta
Tlow
Thigh
Trise
Tfall
Tsusto
Min
-
4000
4700
4000
-
-
4000
Max
400
-
-
-
1000
300
-
Unit
kHz
ns
ns
ns
ns
ns
ns
SDA
SCL
Thdsta
...Trise
...Tlow
Thigh
Figure 3 I2C Mode timing
Tfall
Tsusto
4. I2C Control of NTP3000
All the functions of NTP3000 are controlled by register setting through built-in I2C host interface.
Copyright © NeoFidelity, Inc. 2005
Preliminary datasheet – NeoFidelity reserves the right to change specifications at any time without prior notice
5
R0.73-11.2006
5 Page 
Power Integrated Processor for Digital Amplifier
NTP3000
SDATA
(input)
X X X X X X X X L23 L22 L21 L20 L19 L18 L17 L16 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 X X X X X X X X L23 L22 L21 L20 L19 L18 L17 L16 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
MSB
LSB
Register 1R=eg0is0t0er0100=00100:0R11ig0h1t :jusRtiigfihetdju, sMtifSieBd, fMirSstB, 2fir4sbt,i2t 4bit
MSB
LSB
SDATA
(input)
SDATA
(input)
SDATA
(input)
X X X X X X X X X X X X L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 X X X X X X X X X X X X L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19
LSB MSB
Register 1R=eg0i0st0e0r 011=10100: 0R1i0g1h1t j:usRtiifgiehtdj,usLtSifiBed,firLsStB, 2fi0rsbt,it20bit
LSB
MSB
L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 X X X X X X X X L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 X X X X X X X X
LSB
MSB
LSB
Register 1 = 00000010 : Left justified, LSB first, 24bit
Register 1 = 00001110 : Left justified, LSB first, 24bit
MSB
L23 L22 L21 L20 L19 L18 L17 L16 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 X X X X X X X X L23 L22 L21 L20 L19 L18 L17 L16 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 X X X X X X X X
MSB
LSB MSB
RegisterR1eg=is0te0r010=00000000:11L0e0ft :jusLteifftiejuds,tiMfieSd,BMfSirBstf,ir2st4, b2i4tbit
LSB
Figure 11 General serial audio data formats
7. Mixer
Channel mixer can be used in lots of application needs like bass management, subwoofer signal
generation, pseudo stereo, etc. Mixer cross-connects two input channels to three output channels. Mixer
can control both gain and polarity of each channel input. Step size of mixer gain change is also variable
according to the gain level as shown below.
Table 4 Variable step mixing gain
Volume Range(dB) Step(dB)
+18 ~ + 6
1
+5.5 ~ -5.5
0.5
-6 ~ -32
1
< -32
-∞
In total, 6 mixing gain coefficients denoted as M00, M01, M10,…, M21 are defined as shown in the
equation below. Each Mxx stores volume value in dB scale, and the number values versus gain in dB are
shown in the appendix. There are some places in the mixing matrix that are considered as trivial
connections and thus predefined as -∞ dB.
[Output Channels] = [Mixer Matrix] x [Input Channels]
CH1 OUT
CH2 OUT
CH3 OUT
=
M00 M01
M10 M11
M20 M21
. CH1 IN
CH2 IN
Figure 12 Mixer matrix
Copyright © NeoFidelity, Inc. 2005
Preliminary datasheet – NeoFidelity reserves the right to change specifications at any time without prior notice
11
R0.73-11.2006
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet NTP3000.PDF ] | |
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