PDF IS45S81600E Data sheet ( Hoja de datos )

Número de pieza	IS45S81600E
Descripción	128Mb SYNCHRONOUS DRAM
Fabricantes	Integrated Silicon Solution
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No Preview Available ! IS45S81600E IS45S16800E 1162M8Mxb8S, Y8NMCxH1R6O NOUS DRAM DECEMBER 2011 FEATURES • Clock frequency: 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply IS45S81600E Vdd Vddq 3.3V 3.3V IS45S16800E 3.3V 3.3V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • Auto Refresh (CBR) • Self Refresh • 4096 refresh cycles every 16 ms (A2 grade) or 64 ms (A1 grade) • Random column address every clock cycle • Programmable CAS latency (2, 3 clocks) • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command • Automotive Temperature Range: Option A1: -40oC to +85oC Option A2: -40oC to +105oC OVERVIEW ISSI's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized as follows. IS45S81600E 4M x8 x4 Banks 54-pin TSOPII IS45S16800E 2M x16 x4 Banks 54-pin TSOPII 54-ball BGA KEY TIMING PARAMETERS Parameter Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 -6 -7 6 7 10 10 166 143 100 100 5.4 5.4 6.5 6.5 Unit ns ns Mhz Mhz ns ns Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with- out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com Rev. E 12/01/2011 1 1 page IS45S81600E, IS45S16800E PIN CONFIGURATION 54-ball BGA for x16 (Top View) (8.00 mm x 8.00 mm Body, 0.8 mm Ball Pitch) package code: 54B (8x8) 123456789 A B VSS DQ15 VSSQ C DQ14 DQ13 VDDQ D DQ12 DQ11 VSSQ E DQ10 DQ9 VDDQ F DQ8 NC VSS G DQMH CLK CKE H NC A11 A9 J A8 A7 A6 VSS A5 A4 VDDQ DQ0 VDD VSSQ DQ2 DQ1 VDDQ DQ4 DQ3 VSSQ DQ6 DQ5 VDD DQML DQ7 CAS RAS WE BA0 BA1 CS A0 A1 A10 A3 A2 VDD PIN DESCRIPTIONS A0-A11 Row Address Input A0-A8 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ15 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command CAS Column Address Strobe Command WE DQML DQMH Vdd Vss Vddq Vssq NC Write Enable x16 Lower Byte Input/Output Mask x16 Upper Byte Input/Output Mask Power Ground Power Supply for I/O Pin Ground for I/O Pin No Connection Integrated Silicon Solution, Inc. — www.issi.com Rev. E 12/01/2011 5 5 Page IS45S81600E, IS45S16800E FUNCTIONAL TRUTH TABLE Continued: Current State Read with auto Precharging Write with Auto Precharge Precharging Row Activating CS RAS CAS WE H × × × L H H H L H H L L H L H L H L L L L H H L L H L L L L H L L L L H × × × L H H H L H H L L H L H L H L L L L H H L L H L L L L H L L L L H × × × L H H H L H H L L H L H L H L L L L H H L L H L L L L H L L L L H × × × L H H H L H H L L H L H L H L L L L H H L L H L L L L H L L L L Address × x × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × OC, BA × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × OC, BA × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × OC, BA × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × OC, BA Command DESL Action Continue burst to end, Precharge NOP BST READ/READA WRIT/ WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/ WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Continue burst to end, Precharge ILLEGAL ILLEGAL (11) ILLEGAL (11) ILLEGAL (3) ILLEGAL (11) ILLEGAL ILLEGAL Continue burst to end, Write recovering with auto precharge Continue burst to end, Write recovering with auto precharge ILLEGAL ILLEGAL(11) ILLEGAL (11) ILLEGAL (3,11) ILLEGAL (3,11) ILLEGAL ILLEGAL Nop, Enter idle after tRP Nop, Enter idle after tRP Nop, Enter idle after tRP ILLEGAL (3) ILLEGAL (3) ILLEGAL(3) Nop Enter idle after tRP ILLEGAL ILLEGAL Nop, Enter bank active after tRCD Nop, Enter bank active after tRCD Nop, Enter bank active after tRCD ILLEGAL (3) ILLEGAL (3) ILLEGAL (3,9) ILLEGAL (3) ILLEGAL ILLEGAL Note: H=Vih, L=Vil x= Vih or Vil, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code Integrated Silicon Solution, Inc. — www.issi.com Rev. E 12/01/2011 11 11 Page

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Número de pieza	Descripción	Fabricantes
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