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74ALVC32 PDF даташит

Спецификация 74ALVC32 изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «Quad 2-input OR gate».

Детали детали

Номер произв 74ALVC32
Описание Quad 2-input OR gate
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74ALVC32 Даташит, Описание, Даташиты
74ALVC32
Quad 2-input OR gate
Rev. 3 — 20 January 2014
Product data sheet
1. General description
The 74ALVC32 is a quad 2-input OR gate.
Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times.
2. Features and benefits
Wide supply voltage range from 1.65 V to 3.6 V
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 V to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
Complies with JEDEC standards:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
74ALVC32D 40 C to +85 C SO14
plastic small outline package; 14 leads;
body width 3.9 mm
74ALVC32PW 40 C to +85 C
TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
74ALVC32BQ 40 C to +85 C
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
Version
SOT108-1
SOT402-1
SOT762-1









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74ALVC32 Даташит, Описание, Даташиты
NXP Semiconductors
4. Functional diagram
74ALVC32
Quad 2-input OR gate
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Fig 1. Logic symbol
< 
< 
< 
< 
PQD

•


 •


 •


 • 

PQD
Fig 2. IEC logic symbol
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Fig 3. Logic diagram (one gate)
5. Pinning information
5.1 Pinning
<
PQD
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 VCC
13 4B
12 4A
32 11 4Y
10 3B
9 3A
8 3Y
001aad101
Fig 4. Pin configuration SO14 and TSSOP14
terminal 1
index area
1B 2
1Y 3
2A 4
2B 5
2Y 6
32
GND(1)
13 4B
12 4A
11 4Y
10 3B
9 3A
001aad102
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration DHVQFN14
74ALVC32
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 20 January 2014
© NXP B.V. 2014. All rights reserved.
2 of 14









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74ALVC32 Даташит, Описание, Даташиты
NXP Semiconductors
74ALVC32
Quad 2-input OR gate
5.2 Pin description
Table 2.
Symbol
nA
nB
nY
VCC
GND
Pin description
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
14
7
6. Functional description
Description
data input
data input
data output
supply voltage
ground (0 V)
Table 3. Function table[1]
Input nA
L
L
H
H
[1] H = HIGH voltage level
L = LOW voltage level
7. Limiting values
Input nB
L
H
L
H
Output nY
L
H
H
H
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max
Unit
VCC supply voltage
0.5 +4.6
V
IIK
input clamping current
VI < 0 V
50 -
mA
VI input voltage
0.5 +4.6
V
IOK
output clamping current
VO > VCC or VO < 0 V
- 50
mA
VO output voltage
output HIGH or LOW state
[1] [2] 0.5
VCC + 0.5 V
output 3-state
0.5 +4.6
V
power-down mode, VCC = 0 V
[2] 0.5
+4.6
V
IO output current
VO = 0 V to VCC
- 50
mA
ICC
IGND
Tstg
Ptot
supply current
ground current
storage temperature
total power dissipation
Tamb = 40 C to +85 C
-
100
65
[3] -
100
-
+150
500
mA
mA
C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (power-down mode), the output voltage can be 3.6 V in normal operation.
[3] For SO14 packages: above 70 C derate linearly with 8 mW/K.
For TSSOP14 packages: above 60 C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 C derate linearly with 4.5 mW/K.
74ALVC32
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 20 January 2014
© NXP B.V. 2014. All rights reserved.
3 of 14










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