PDF H5TS5163MFR-NOC Data sheet ( Hoja de datos )

Número de pieza	H5TS5163MFR-NOC
Descripción	512Mb DDR3 SDRAM
Fabricantes	Hynix Semiconductor
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No Preview Available ! H5TQ(S)5163MFR 512Mb DDR3 SDRAM H5TQ(S)5163MFR Since DDR3 Specification has not been defined completely yet in JEDEC, this document may contain items under discussion. Contents may be changed at any time without any notice. Rev. 1.0 / Oct 2008 This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. 1 1 page H5TQ(S)5163MFR DESCRIPTION The H5TQ(S)5163MFR is a 1,073,741,824-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. Hynix 512Mb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. 1.1 Device Features and Ordering Information . FEATURES • VDD/VDDQ=1.5V +/- 0.075V VDD/VDDQ=1.8V +/- 0.09V • Fully differential clock inputs (CK, /CK) operation • Differential Data Strobe (DQS, /DQS) • On chip DLL align DQ, DQS and /DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11) supported • Programmable additive latency 0, CL-1, and CL-2 supported • Programmable CAS Write latency (CWL) = 5, 6, 7, 8 • Programmable burst length 4/8 with both nibble sequential and interleave mode • BL switch on the fly • 8banks • 8K refresh cycles /64ms • JEDEC standard 96ball FBGA • Driver strength selected by EMRS • Dynamic On Die Termination supported • Asynchronous RESET pin supported • ZQ calibration supported • Write Levelization supported • Auto Self Refresh supported • On Die Thermal Sensor supported ( JEDEC optional ) • 8 bit pre-fetch . ORDERING INFORMATION Part No. H5TS5163MFR-NOC H5TS5163MFR-11C H5TS5163MFR-12C H5TS5163MFR-14C H5TQ5163MFR-12C H5TQ5163MFR-14C H5TQ5163MFR-16C H5TQ5163MFR-20C Power Supply VDD/VDDQ =1.8V VDD/VDDQ =1.5V Clock Frequency 1GHz 900MHz 800MHz 700MHz 800MHz 700MHz 600MHz 500MHz Max Data Rate 2Gbps/pin 1.8Gbps/pin 1.6Gbps/pin 1.4Gbps/pin 1.6Gbps/pin 1.4Gbps/pin 1.2Gbps/pin 1.0Gbps/pin Interface SSTL-18 SSTL-15 Package 96Ball FBGA Note) Hynix supports Halogen free parts for each speed grade with same specification, except Halogen free materials. We’ll add “R” character after “F” for Halogen free product. For example, the part number of 500MHz Halogen free product is H5TQ5163MFR-20C. Rev. 1.0 / Oct 2008 5 5 Page H5TQ(S)5163MFR 1.6 DDR3 SDRAM Mode Register (MR0) The mode register stores the data for controlling the various operating modes of DDR3 SDRAM. It controls burst length, read burst type, CAS latency, test mode, DLL reset, WR and DLL control for precharge Power- Down, which include various vendor specific options to make DDR3 SDRAM useful for various applications. The mode register is written by asserting low on CS#, RAS#, CAS#, WE#, BA0, BA1, and BA2, while control- ling the states of address pins according to Figure 6. BA2 BA1 BA0 A15 ~ A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field 01 0 0 01 PPD WR DLL TM CAS Latency RBT CL BL Mode Register 0 A8 DLL Reset 0 No 1 Yes A12 DLL Control for Precharge PD 0 Slow exit (DLL off) 1 Fast exit (DLL on) BA1 BA0 00 01 10 11 MR Select MR0 MR1 MR2 MR3 A7 mode 0 Normal 1 Test A3 Read Burst Type Burst Length 0 Sequential A2 A1 A0 1 Interleave 00 8 (Fixed) 0 1 BC4 of 8(on the fly) 10 BC4 (Fixed) 11 Reserved Write recovery for autoprecharge CAS Latency A11 A10 A9 WR(cycles) 0 00 Reserved 0 01 52 0 10 62 0 11 72 1 00 82 1 01 102 1 10 122 1 11 Reserved A6 A5 A4 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 A2 Latency 0 Reserved 05 06 07 08 09 0 10 0 11 (Optional for DDR3-1600) 1 : BA2 and A13~A15 are RFU and must be programmed to 0 during MRS. 2: WR(write recovery for autoprecharge) min in clock cycles is calculated by dividing tWR(in ns) by tCK(in ns) and rounding up to the next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR value in the mode register must be programmed to be equal or larger than WRmin. The programmed WR value is used with tRP to determine tDAL. Figure 6. DDR3 SDRAM mode register set (MR0) Rev. 1.0 / Oct 2008 11 11 Page

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