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H5TQ5163MFR-12 PDF даташит

Спецификация H5TQ5163MFR-12 изготовлена ​​​​«Hynix Semiconductor» и имеет функцию, называемую «512Mb DDR3 SDRAM».

Детали детали

Номер произв H5TQ5163MFR-12
Описание 512Mb DDR3 SDRAM
Производители Hynix Semiconductor
логотип Hynix Semiconductor логотип 

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H5TQ5163MFR-12 Даташит, Описание, Даташиты
H5TQ(S)5163MFR
512Mb DDR3 SDRAM
H5TQ(S)5163MFR
** Since DDR3 Specification has not been defined completely yet
in JEDEC, this document may contain items under discussion.
** Contents may be changed at any time without any notice.
Rev. 1.0 / Oct 2008
This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
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H5TQ5163MFR-12 Даташит, Описание, Даташиты
Revision History
Revision No.
History
0.1 Preliminary
0.2 Async/Sync Parameter addition
0.3 1) (sub)Part number change as Hynix New naming system
2) CL change at 800MHz (to 12clock)
0.4 1) 1.8V version insert
2) CL change at 800MHz (to 11clock)
0.5 Typo Change
0.6 Inserted IDD SPEC.
1.0 IDD change
H5TQ(S)5163MFR
Draft Date
Jan. 2008
Mar. 2008
May 2008
Remark
Preliminary
Preliminary
May 2008
May 2008
July 2008
Oct 2008
Preliminary
Preliminary
Preliminary
Rev. 1.0 / Oct 2008
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H5TQ5163MFR-12 Даташит, Описание, Даташиты
H5TQ(S)5163MFR
Table of Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Description
1.1.2 Features
1.1.3 Ordering Information
1.1.4 Ordering Frequency
1.2 Package Ballout
1.3 Row and Column Address Table : 512M/1G Fixed
1.4 Pin Functional Description
1.5 Programming the Mode Registers
1.6 DDR3 SDRAM Mode Register(MR0)
1.6.1 Burst Length, Type and Order
1.6.2 CAS Latency
1.6.3 Test Mode
1.6.4 DLL Reset
1.6.5 Write Recovery
1.6.6 Precharge PD DLL
1.7 DDR3 SDRAM Mode Register(MR1)
1.7.1 DLL Enable/Disable
1.7.2 Output Driver Impedance Control
1.7.3 ODT Rtt Values
1.7.4 Additive Latency(AL)
1.7.5 Write leveling
1.7.6 Output Disable
1.7.7 TDQS, /TDQS
1.8 DDR3 SDRAM Mode Register(MR2)
1.8.1 Partial Array Self-Refresh(PASR)
1.8.2 CAS Write Latency(CWL)
1.8.3 Auto SElf-Refresh(ASR) and Self-Refresh Temperature(SRT)
1.8.4 Dynamic ODT(Rtt_WR)
1.9 DDR3 SDRAM Mode Register(MR3)
1.9.1 Multi-Purposer Register(MPR)
2. Command Description
2.1 Command Truth Table
2.2 Clock Enable (CKE) Truth Table for Synchronous Transitions
3. Absolute Maximum Ratings
4. Operating Conditions
4.1 Operating Temperature Condition
4.2 DC Operating Conditions
5. AC and DC Input Measurement Levels
5.1 AC and DC Logic Input Levels for Single-Ended Signals
5.2 AC and DC Logic Input Levels for Differential Signals
5.3 Differential Input Cross Point Voltage
5.4 Slew Rate Definitions for Single Ended Input Signals
5.4.1 Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS)
5.4.2 Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH)
Rev. 1.0 / Oct 2008
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