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25l6445E PDF даташит

Спецификация 25l6445E изготовлена ​​​​«MACRONIX» и имеет функцию, называемую «MX25l6445E».

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Номер произв 25l6445E
Описание MX25l6445E
Производители MACRONIX
логотип MACRONIX логотип 

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25l6445E Даташит, Описание, Даташиты
MX25L6445E
MX25L6445E
HIGH PERFORMANCE
SERIAL FLASH SPECIFICATION
P/N: PM1736
REV. 1.8, DEC. 26, 2011
1









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25l6445E Даташит, Описание, Даташиты
MX25L6445E
Contents
FEATURES................................................................................................................................................................... 5
GENERAL DESCRIPTION.......................................................................................................................................... 7
Table 1. Additional Features ............................................................................................................................... 7
PIN CONFIGURATION................................................................................................................................................. 8
PIN DESCRIPTION....................................................................................................................................................... 8
BLOCK DIAGRAM....................................................................................................................................................... 9
DATA PROTECTION.................................................................................................................................................. 10
Table 2. Protected Area Sizes........................................................................................................................... 11
Table 3. 4K-bit Secured OTP Definition............................................................................................................ 11
Memory Organization............................................................................................................................................... 12
Table 4. Memory Organization.......................................................................................................................... 12
DEVICE OPERATION................................................................................................................................................. 13
Figure 1-1. Serial Modes Supported (for Normal Serial mode)......................................................................... 13
Figure 1-2. Serial Modes Supported (for Double Transfer Rate serial read mode).......................................... 13
COMMAND DESCRIPTION....................................................................................................................................... 14
Table 5. Command Sets.................................................................................................................................... 14
(1) Write Enable (WREN).................................................................................................................................. 16
(2) Write Disable (WRDI).................................................................................................................................. 16
(3) Read Identification (RDID)........................................................................................................................... 16
(4) Read Status Register (RDSR)..................................................................................................................... 17
(5) Write Status Register (WRSR).................................................................................................................... 18
Protection Modes.............................................................................................................................................. 18
(6) Read Data Bytes (READ)............................................................................................................................ 19
(7) Read Data Bytes at Higher Speed (FAST_READ)...................................................................................... 19
(8) Fast Double Transfer Rate Read (FASTDTRD).......................................................................................... 19
(9) 2 x I/O Read Mode (2READ)....................................................................................................................... 19
(10) 2 x I/O Double Transfer Rate Read Mode (2DTRD).................................................................................. 20
(11) 4 x I/O Read Mode (4READ)..................................................................................................................... 20
(12) 4 x I/O Double Transfer Rate Read Mode (4DTRD).................................................................................. 21
(13) Sector Erase (SE)...................................................................................................................................... 21
(14) Block Erase (BE)....................................................................................................................................... 22
(15) Block Erase (BE32K)................................................................................................................................. 22
(16) Chip Erase (CE)........................................................................................................................................ 22
(17) Page Program (PP)................................................................................................................................... 23
(18) 4 x I/O Page Program (4PP)...................................................................................................................... 23
Program/Erase Flow(1) with read array data.................................................................................................... 24
Program/Erase Flow(2) without read array data............................................................................................... 25
(19) Continuously program mode (CP mode)................................................................................................... 26
(20) Deep Power-down (DP)............................................................................................................................. 27
(21) Release from Deep Power-down (RDP), Read Electronic Signature (RES)............................................. 27
(22) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4), (REMS4D)........................ 27
Table 6. ID Definitions ...................................................................................................................................... 28
(23) Enter Secured OTP (ENSO)...................................................................................................................... 28
(24) Exit Secured OTP (EXSO)........................................................................................................................ 28
P/N: PM1736
REV. 1.8, DEC. 26, 2011
2









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25l6445E Даташит, Описание, Даташиты
MX25L6445E
(25) Read Security Register (RDSCUR)........................................................................................................... 28
Security Register Definition............................................................................................................................... 29
(26) Write Security Register (WRSCUR).......................................................................................................... 29
(27) Write Protection Selection (WPSEL)......................................................................................................... 30
BP and SRWD if WPSEL=0.............................................................................................................................. 30
The individual block lock mode is effective after setting WPSEL=1................................................................. 31
WPSEL Flow..................................................................................................................................................... 32
(28) Single Block Lock/Unlock Protection (SBLK/SBULK)................................................................................ 33
Block Lock Flow................................................................................................................................................ 33
Block Unlock Flow............................................................................................................................................. 34
(29) Read Block Lock Status (RDBLOCK)........................................................................................................ 35
(30) Gang Block Lock/Unlock (GBLK/GBULK)................................................................................................. 35
(31) Clear SR Fail Flags (CLSR)...................................................................................................................... 35
(32) Enable SO to Output RY/BY# (ESRY)...................................................................................................... 35
(33) Disable SO to Output RY/BY# (DSRY)..................................................................................................... 35
(34) Read SFDP Mode (RDSFDP)................................................................................................................... 36
POWER-ON STATE.................................................................................................................................................... 42
ELECTRICAL SPECIFICATIONS.............................................................................................................................. 43
ABSOLUTE MAXIMUM RATINGS.................................................................................................................... 43
Figure 2. Maximum Negative Overshoot Waveform......................................................................................... 43
CAPACITANCE TA = 25°C, f = 1.0 MHz........................................................................................................... 43
Figure 3. Maximum Positive Overshoot Waveform........................................................................................... 43
Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL............................................................ 44
Figure 5. OUTPUT LOADING.......................................................................................................................... 44
Table 10. DC CHARACTERISTICS ................................................................................................................. 45
Table 11. AC CHARACTERISTICS................................................................................................................... 46
Timing Analysis......................................................................................................................................................... 48
Figure 6. Serial Input Timing............................................................................................................................. 48
Figure 7. Output Timing.................................................................................................................................... 48
Figure 8. Serial Input Timing for Double Transfer Rate Mode........................................................................... 49
Figure 9. Serial Output Timing for Double Transfer Rate Mode........................................................................ 49
Figure 10. WP# Setup Timing and Hold Timing during WRSR when SRWD=1............................................... 50
Figure 11. Write Enable (WREN) Sequence (Command 06)............................................................................ 50
Figure 12. Write Disable (WRDI) Sequence (Command 04)............................................................................ 50
Figure 13. Read Identification (RDID) Sequence (Command 9F).................................................................... 51
Figure 14. Read Status Register (RDSR) Sequence (Command 05)............................................................... 51
Figure 15. Write Status Register (WRSR) Sequence (Command 01)............................................................. 51
Figure 16. Read Data Bytes (READ) Sequence (Command 03)..................................................................... 52
Figure 17. Read at Higher Speed (FAST_READ) Sequence (Command 0B)................................................. 52
Figure 18. Fast DT Read (FASTDTRD) Sequence (Command 0D)................................................................. 52
Figure 19. 2 x I/O Read Mode Sequence (Command BB)................................................................................ 53
Figure 20. Fast Dual I/O DT Read (2DTRD) Sequence (Command BD).......................................................... 53
Figure 21. 4 x I/O Read Mode Sequence (Command EB)................................................................................ 54
Figure 22. 4 x I/O Read Enhance Performance Mode Sequence (Command EB)........................................... 54
Figure 23. Fast Quad I/O DT Read (4DTRD) Sequence (Command ED)........................................................ 55
Figure 24. Fast Quad I/O DT Read (4DTRD) Enhance Performance Sequence (Command ED)................... 55
P/N: PM1736
REV. 1.8, DEC. 26, 2011
3










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