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PDF W83L951ADG Data sheet ( Hoja de datos )

Número de pieza W83L951ADG
Descripción Mobile Keyboard and Embedded Controller
Fabricantes Winbond　
Logotipo Winbond Logotipo



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No Preview Available ! W83L951ADG Hoja de datos, Descripción, Manual

W83L951ADG
CONSUMER PRODUCT DESCRIPTION
Winbond
Mobile Keyboard and
Embedded Controller
W83L951ADG
Date: November 21, 2007 Reversion: 0.7

1 page




W83L951ADG pdf
W83L951ADG
7.1.11 Slave Status Register (SM0/11SSTS) (Default Value: 0000_0000) .....................................60
7.1.12 Slave FIFO Status Register (SM0/1SFIFOSTS) (Default Value: 0100_0000) ......................61
8. INTERNAL INTERRUPT CONTROLLER BLOCK ........................................................................ 62
8.1 Register Description ............................................................................................................ 64
8.1.1 Interrupt Enable 1 Register (IE1) (Default Value: 0000_0000) .............................................64
8.1.2 Interrupt Enable 2 Register (IE2) (Default Value: 0000_0000) .............................................64
8.1.3 Interrupt Enable 3 Register (IE3) (Default Value: 0000_0000) .............................................64
8.1.4 Interrupt Enable 4 Register (IE4) (Default Value: 0000_0000) .............................................64
8.1.5 Interrupt Request 1 Register (IREQ1) (Default Value: 0000_0000)......................................64
8.1.6 Interrupt Request 2 Register (IREQ2) (Default Value: 0000_0000)......................................65
8.1.7 Interrupt Request 3 Register (IREQ3) (Default Value: 0000_0000)......................................65
8.1.8 Interrupt Request 4 Register (IREQ4) (Default Value: 0000_0000)......................................65
8.1.9 Interrupt Priority 1 Register (IP1) (Default Value: 0000_0000) .............................................65
8.1.10 Interrupt Priority 2 Register (IP2) (Default Value: 0000_0000) .............................................66
8.1.11 Interrupt Priority 3 Register (IP3) (Default Value: 0000_0000) .............................................66
8.1.12 Interrupt Priority 4 Register (IP4) (Default Value: 0000_0000) .............................................66
9. GPIOS BLOCK .............................................................................................................................. 67
9.1 GPIO Data Register Description ......................................................................................... 68
9.1.1 GPIO 0 Input/Output Register (GPIO0) (Default Value: 0000_0000)....................................68
9.1.2 GPIO 1 Input/Output Register (GPIO1) (Default Value: 0000_0000)....................................69
9.1.3 GPIO 2 Input/Output Register (GPIO2) (Default Value: 0000_0000)....................................69
9.1.4 GPIO 3 Input/Output Register (GPIO3) (Default Value: 0000_0000)....................................69
9.1.5 GPIO 4 Input/Output Register (GPIO4) (Default Value: 0000_0000)....................................69
9.1.6 GPIO 5 Input/Output Register (GPIO5) (Default Value: 0000_0000)....................................70
9.1.7 GPIO 6 Input/Output Register (GPIO6) (Default Value: 0000_0000)....................................70
9.1.8 GPIO 7 Input/Output Register (GPIO7) (Default Value: 0000_0000)....................................70
9.1.9 GPIO 8 Input/Output Register (GPIO8) (Default Value: 0000_0000)....................................70
9.1.10 GPIO 9 Input/Output Register (GPIO9) (Default Value: 0000_0000)....................................71
9.1.11 GPIO A Input/Output Register (GPIOA) (Default Value: 0000_0000)...................................71
9.1.12 GPIO B Input/Output Register (GPIOB) (Default Value: 0000_0000)...................................71
9.1.13 GPIO C Input/Output Register (GPIOC) (Default Value: 0000_0000) ..................................71
9.2 GPIO Direction Register Description................................................................................... 72
9.2.1 GPIO 0 Direction Register (GPIOD0) (Default Value: 0000_0000).......................................72
9.2.2 GPIO 1 Direction Register (GPIOD1) (Default Value: 0000_0000).......................................72
9.2.3 GPIO 2 Direction Register (GPIOD2) (Default Value: 0000_0000).......................................72
9.2.4 GPIO 3 Direction Register (GPIOD3) (Default Value: 0000_0000).......................................72
9.2.5 GPIO 4 Direction Register (GPIOD4) (Default Value: 0000_0000).......................................72
9.2.6 GPIO 5 Direction Register (GPIOD5) (Default Value: 0000_0000).......................................72
9.2.7 GPIO 6 Direction Register (GPIOD6) (Default Value: 0000_0000).......................................72
9.2.8 GPIO 7 Direction Register (GPIOD7) (Default Value: 0000_0000).......................................72
Publication Release Date: Nov. 21, 2007
- 5 - Revision 0.7

5 Page





W83L951ADG arduino
2. PIN CONFIGURATION
2.1 128-Pin Low Profile Quad Flat Pack (LQFP)
W83L951ADG
GP35/M_KR5/FWEN#/(FD5)
GP34/M_KR4/ALE(FD4)
GP33/M_KR3/TS(FD3)
GP32/M_KR2/(FD2)
GP31/M_KR1/(FD1)
GP30/M_KR0/(FD0)
VREF
AD7/GP67
AD6/GP66
AD5/GP65
AD4/GP64
AD3/GP63
AD2/GP62
AD1/GP61
AD0/GP60
AVCC
DA2/GP57
DA1/GP56
AGND
GP55
GP54
SCK/GP53
MISO/GP52
MOSI/GP51
SCS/GP50
XOUT
XIN
TEST#
XCOUT
XCIN
EXTINT37/GPC7
EXTINT36/GPC6
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
W83L951ADG
64 GP44/KBRST#
63 GP45/GATE_A20
62 GP46/CLKRUN#
61 GP47
60 LPCSTS
59 LAD3
58 LAD2
57 LAD1
56 LAD0
55 GND
54 SERIRQ
53 LRESET#
52 LFRAME#
51 LCLK
50 RESET#
49 VCC1
48 GP70/KPS2CLK
47 GP71/KPS2DAT
46 GP72/MPS2CLK
45 GP73/MPS2DAT
44 GP74
43 GP75
42 GP76/SDA0
41 GP77/SCL0
40 GP80/SDA1
39 GP81/SCL1
38 CNTR0/GP82
37 CNTR1/GP83
36 CIR_RX/GP84
35 GP85
34
33
GP86
GP87
Figure 2-1.Pin Configuration Block Diagram of W83L951ADG
Note: The Pin Configuration is only for 128-pin LQFP Package.
- 11 -
Publication Release Date: Nov. 21, 2007
Revision 0.7

11 Page







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