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PDF 74LVC373A Data sheet ( Hoja de datos )
| Número de pieza | 74LVC373A | |
| Descripción | OCTAL TRANSPARENT D-TYPE LATCH | |
| Fabricantes | Diodes | |
| Logotipo |  |
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74LVC373A
OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
Description
The 74LVC373A provides eight transparent D-type latches. While the
latch-enable (LE) input is high, the Q outputs follow the data (D)
inputs. When LE is taken low, the Q outputs are latched at the logic
levels set up at the D inputs. A buffered output-enable (OE) input can
be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus lines significantly. The
high-impedance state and increased drive provide the capability to
drive bus lines without interface or pullup components. OE does not
affect the internal operations of the latches. Old data can be retained
or new data can be entered while the outputs are in the high-
impedance state.
The device is designed for operation with a power supply range of
1.65V to 3.6V.
The inputs are tolerant to 5.5V allowing this device to be used in a
mixed voltage environment. The device is fully specified for partial
power down applications using IOFF. The IOFF circuitry disables the
output preventing damaging current backflow when the device is
powered down.
Features
• Supply Voltage Range from 1.65V to 3.6V
• Sinks or Sources 24mA at VCC = 3V
• CMOS Low Power Consumption
• IOFF Supports Partial Power Down Operation
• Inputs or Outputs Accept Up to 5.5V
• Inputs Can Be Driven by 3.3V or 5V Allowing for Mixed Voltage
Applications
• Schmitt Trigger Action at All Inputs
• Typical VOLP (Quiet Output Ground Bounce) Less Than 0.8V with
VCC = 3.3V and TA = +25°C
• Typical VOHV (Quiet Output dynamic VOH) Greater than 2.0V with
VCC = 3.3V and TA = +25°C
• ESD Protection Tested per JESD 22
Exceeds 200-V Machine Model (A115)
Exceeds 2000-V Human Body Model (A114)
Exceeds 1000-V Charged Device Model (C101)
• Latch-Up Exceeds 250mA per JESD 78, Class II
• All devices are:
Totally Lead-Free & Fully RoHS compliant (Notes 1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
Pin Assignments
Applications
• General Purpose Logic
• Bus Driving
• Power Down Signal Isolation
• Wide array of products such as:
PCs, Notebooks, Netbooks, Ultrabooks
Networking Computer Peripherals, Hard Drives, CD/DVD
ROM
TV, DVD, DVR, Set Top Box
Notes:
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen and Antimony free,
"Green" and Lead-Free.
3. Halogen and Antimony free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
74LVC373A
Document number: DS35893 Rev. 1 - 2
1 of 10
www.diodes.com
June 2014
© Diodes Incorporated
1 page  
74LVC373A
Switching Characteristics
Symbol
tW
tSU
tH
tPD
tPD
tEN
tDIS
tDIS
tsk(0)
Parameter
Pulse Width
LE
Test
Conditions
Figure 1
Set-up Time DN to
LE
Figure 1
Hold Time
DN to LE
Figure 1
Propagation Delay
DN to QN
Figure 1
Propagation Delay
LE to QN
Figure 1
Enable Time
OE to QN
Figure 1
Disable Time
OE to QN
Figure 1
Disable Time
OE to QN
Output Skew Time
Figure 1
Vcc
1.8V ± 0.15V
2.5V ± 0.3V
2.7V
3.3V ± 0.3
1.8V ± 0.15V
2.5V ± 0.3V
2.7V
3.3V ± 0.3
1.8V ± 0.15V
2.5V ± 0.3V
2.7V
3.3V ± 0.3
1.8V ± 0.15V
2.5V ± 0.3V
2.7V
3.3V ± 0.3
1.8V ± 0.15V
2.5V ± 0.3V
2.7V
3.3V ± 0.3
1.8V ± 0.15V
2.5V ± 0.3V
2.7V
3.3V ± 0.3
1.8V ± 0.15V
2.5V ± 0.3V
2.7V
3.3V ± 0.3
1.8V ± 0.15V
2.5V ± 0.3V
2.7V
3.3V ± 0.3V
3.3V ± 0.3V
TA = +25°C
Min Typ. Max
5.0 2.5
4.0 2.0
3.0 1.7
3.0 1.5
4.0 2.0
3.0 1.5
2.0 1.0
2.0 1.0
3.0 1.5
2.0 1.0
1.5 1.0
1.5 1.0
1 6 12.2
1 3.9 7.8
1 4.2 7.8
1.5 3.8 6.8
1 7 14.8
1 4.5 10
1 5.4 8.2
1.5 4.4 7.2
1 7.8 16.5
149
1 4.4 8.3
1.7 4.1 7.3
1 7.8 16.5
149
1 4.4 8.3
1.7 4.1 7.3
1 7.8 16.5
149
1 4.4 8.3
1.7 4.1 7.3
1.0
-40°C to +85°C
Min Max
5.0
4.0
3.0
3.0
4.0
3.0
2.0
2.0
3.0
2.0
1.5
1.5
1 12.7
1 8.3
1 7.3
1.5 6.3
1 15.3
1 10.5
1 9.5
1.5 8.5
1 17
1 9.5
1 8.5
1.7 7.5
1 17
1 9.5
1 8.5
1.7 7.5
1 17
1 9.5
1 8.5
1.7 7.5
+85°C to +125°C
Min Max
5.5
4.5
3.5
3.5
4.5
3.5
2.5
2.5
3.5
2.5
2.0
2.0
1 16.9
1 8.7
1 9.5
1.5 8.0
1 22.5
1 12.4
1 12.0
1.5 11.0
1 14.2
1 8.2
1 10.0
1.7 9.0
1 14.2
1 8.2
1 10.0
1.7 9.0
1 14.2
1 8.2
1 10.0
1.7 9.0
1.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Operating Characteristics
TA = +25°C
Symbol
Parameter
Test Conditions
Cpd
Power dissipation
F = 10MHz
capacitance per gate Outputs Enabled
VCC
1.8V ± 0.15V
2.5V ± 0.3V
3.3V ± 0.3V
Typ
9.9
10.2
10.6
Unit
pF
Package Characteristics
Symbol
θJA
θJC
θJA
θJC
Parameter
Thermal Resistance
Junction-to-Ambient
Thermal Resistance
Junction-to-Case
Thermal Resistance
Junction-to-Ambient
Thermal Resistance
Junction-to-Case
Package
TSSOP-20
Test Conditions
Min
Typ
Max Unit
(Note 9)
— 74 — °C/W
TSSOP-20
(Note 9)
— 15 — °C/W
V-QFN4525-20
(Note 9)
— 67 — °C/W
V-QFN4525-20
(Note 9)
— 20 — °C/W
Note:
9. Test conditions for TSSOP-20 and V-QFN4525-20: Devices mounted on 4 layer FR-4 substrate PC board, 2oz copper, with minimum recommended
pad layout per JESD 51-7.
74LVC373A
Document number: DS35893 Rev. 1 - 2
5 of 10
www.diodes.com
June 2014
© Diodes Incorporated
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74LVC373A.PDF ] | |
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