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CAT24C32 PDF даташит

Спецификация CAT24C32 изготовлена ​​​​«ON Semiconductor» и имеет функцию, называемую «32kb I2C CMOS Serial EEPROM».

Детали детали

Номер произв CAT24C32
Описание 32kb I2C CMOS Serial EEPROM
Производители ON Semiconductor
логотип ON Semiconductor логотип 

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CAT24C32 Даташит, Описание, Даташиты
CAT24C32
32-Kb I2C CMOS Serial
EEPROM
Description
The CAT24C32 is a 32−Kb CMOS Serial EEPROM devices,
internally organized as 4096 words of 8 bits each.
It features a 32−byte page write buffer and supports the Standard
(100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C protocol.
External address pins make it possible to address up to eight
CAT24C32 devices on the same bus.
Features
Supports Standard, Fast and Fast−Plus I2C Protocol
1.7 V to 5.5 V Supply Voltage Range
32−Byte Page Write Buffer
Hardware Write Protection for Entire Memory
Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Range
PDIP, SOIC, TSSOP, UDFN, US 8−lead, WLCSP 4−ball and 5−ball
Packages
This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
www.onsemi.com
SOIC−8
W SUFFIX
CASE 751BD
UDFN8
HU4 SUFFIX
CASE 517AZ
US8 *
US SUFFIX
CASE 493
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
WLCSP5
C5A SUFFIX
CASE 567JQ
WLCSP4
C4C SUFFIX
CASE 567JY
PIN CONFIGURATIONS (Top Views)
12 3
1
VCC
2
VSS A
SCL SDA B
WLCSP4 (C4C)
VCC VSS
SDA
WP SCL
A
B
C
WLCSP5 (C5A)
1
A0
VCC
A1 WP
A2 SCL
VSS SDA
PDIP (L), SOIC (W), TSSOP (Y),
US (US), UDFN (HU4)
For the location of Pin 1, please consult the
corresponding package drawing.
* In Development; please contact factory for availability
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
June, 2015 − Rev. 24
1
Publication Order Number:
CAT24C32/D









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CAT24C32 Даташит, Описание, Даташиты
(PDIP−8)
CAT24C32
DEVICE MARKINGS
(SOIC−8)
24C32F
AXXX
YYWWG
24C32F
AYMXXX
24C32F = Specific Device Code
A = Assembly Location
XXX = Last Three Digits of Assembly Lot Number
YY = Production Year (Last Two Digits)
WW = Production Week (Two Digits)
G = Pd−Free designator
(WLCSP−5)
2
YM
2 = Specific Device Code
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
(TSSOP−8)
C32F
AYMXXX
C32F
A
Y
M
XXX
= Specific Device Code
= Assembly Location
= Production Year (Last Digit)
= Production Month (1−9, O, N, D)
= Last Three Digits of Assembly Lot Number
VCC
SCL
A2, A1, A0
WP
CAT24C32
SDA
VSS
Figure 1. Functional Symbol
24C32F = Specific Device Code
A = Assembly Location
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
XXX = Last Three Digits of Assembly Lot Number
(WLCSP−4)
B
YM
B = Specific Device Code
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
(UDFN−8)
C5U
AXX
YM
C5U
A
XX
Y
M
= Specific Device Code
= Assembly Location
= Last Two Digits of Assembly Lot Number
= Production Year (Last Digit)
= Production Month (1−9, O, N, D)
PIN FUNCTION
Pin Name
A0, A1, A2
SDA
SCL
Function
Device Address
Serial Data
Serial Clock
WP Write Protect
VCC Power Supply
VSS Ground
www.onsemi.com
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CAT24C32 Даташит, Описание, Даташиты
CAT24C32
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Storage Temperature
–65 to +150
°C
Voltage on any Pin with Respect to Ground (Note 1)
–0.5 to +6.5
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
Parameter
Min Units
NEND (Note 3) Endurance
1,000,000
Program/Erase Cycles
TDR Data Retention
100 Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, VCC = 5 V, 25°C.
Table 3. D.C. OPERATING CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min Max
Units
ICCR
Read Current
Read, fSCL = 400 kHz
1 mA
ICCW
Write Current
Write, fSCL = 400 kHz
2 mA
ISB Standby Current
All I/O Pins at GND or VCC
TA = −40°C to +85°C
VCC 3.3 V
1 mA
TA = −40°C to +85°C
VCC > 3.3 V
3
TA = −40°C to +125°C
5
IL I/O Pin Leakage
Pin at GND or VCC
2 mA
VIL Input Low Voltage
−0.5
VCC x 0.3
V
VIH Input High Voltage SCL, SDA Inputs
VCC x 0.7
6.5
V
WP, A0, A1, A2 Inputs
VCC x 0.7
VCC + 0.5
VOL1
Output Low Voltage
VCC 2.5 V, IOL = 3.0 mA
0.4 V
VOL2
Output Low Voltage
VCC < 2.5 V, IOL = 1.0 mA
0.2 V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 4. PIN IMPEDANCE CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Max
Units
CIN (Note 4) SDA I/O Pin Capacitance
VIN = 0 V, TA = 25°C, f = 1.0 MHz
8 pF
CIN (Note 4) Input Capacitance (other pins)
VIN = 0 V, TA = 25°C, f = 1.0 MHz
6 pF
IWP (Note 5) WP Input Current
VIN < VIH, VCC = 5.5 V
130 mA
VIN < VIH, VCC = 3.3 V
120
VIN < VIH, VCC = 1.7 V
80
VIN > VIH
2
IA (Note 5)
Address Input Current
(A0, A1, A2)
Product Rev F
VIN < VIH, VCC = 5.5 V
VIN < VIH, VCC = 3.3 V
VIN < VIH, VCC = 1.7 V
50 mA
35
25
VIN > VIH
2
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source.
www.onsemi.com
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