CAT25320 PDF даташит
Спецификация CAT25320 изготовлена «ON Semiconductor» и имеет функцию, называемую «32Kb SPI Serial CMOS EEPROM». |
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Детали детали
Номер произв | CAT25320 |
Описание | 32Kb SPI Serial CMOS EEPROM |
Производители | ON Semiconductor |
логотип |
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CAT25320
32-Kb SPI Serial CMOS
EEPROM
Description
The CAT25320 is a 32−Kb Serial CMOS EEPROM device
internally organized as 4096x8 bits. This features a 32−byte page write
buffer and supports the Serial Peripheral Interface (SPI) protocol. The
device is enabled through a Chip Select (CS) input. In addition, the
required bus signals are clock input (SCK), data input (SI) and data
output (SO) lines. The HOLD input may be used to pause any serial
communication with the CAT25320 device. The device features
software and hardware write protection, including partial as well as
full array protection.
Features
• 10 MHz SPI Compatible
• 1.8 V to 5.5 V Supply Voltage Range
• SPI Modes (0,0) & (1,1)
• 32−byte Page Write Buffer
• Self−timed Write Cycle
• Hardware and Software Protection
• Block Write Protection
− Protect 1/4, 1/2 or Entire EEPROM Array
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• Industrial and Extended Temperature Range
• PDIP, SOIC, TSSOP 8−lead, TDFN and UDFN 8−pad Packages
• This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
VCC
SI
CS
WP
HOLD
SCK
CAT25320
SO
VSS
Figure 1. Functional Symbol
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SOIC−8
V SUFFIX
CASE 751BD
UDFN−8
HU3 SUFFIX
CASE 517AX
TDFN−8*
VP2 SUFFIX
CASE 511AK
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
PIN CONFIGURATION
CS 1
SO
VCC
HOLD
WP SCK
VSS SI
PDIP (L), SOIC (V), TSSOP (Y),
TDFN (VP2*), UDFN (HU3)
* Not recommended for new designs
Pin Name
CS
SO
WP
VSS
SI
SCK
HOLD
VCC
PIN FUNCTION
Function
Chip Select
Serial Data Output
Write Protect
Ground
Serial Data Input
Serial Clock
Hold Transmission Input
Power Supply
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
July, 2015 − Rev. 11
1
Publication Order Number:
CAT25320/D
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CAT25320
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Operating Temperature
Ratings
−45 to +130
Units
°C
Storage Temperature
−65 to +150
°C
Voltage on any Pin with Respect to Ground (Note 1)
−0.5 to +6.5
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
Parameter
Min Units
NEND (Note 3) Endurance
1,000,000
Program / Erase Cycles
TDR Data Retention
100 Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, VCC = 5 V, 25°C.
Table 3. D.C. OPERATING CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min Max
Units
ICCR
Supply Current
(Read Mode)
Read, VCC = 5.5 V,
SO open
10 MHz / −40°C to 85°C
5 MHz / −40°C to 125°C
2 mA
2 mA
ICCW
Supply Current
(Write Mode)
Write, VCC = 5.5 V,
SO open
10 MHz / −40°C to 85°C
5 MHz / −40°C to 125°C
2 mA
3 mA
ISB1 Standby Current
VIN = GND or VCC, CS = VCC,
WP = VCC, VCC = 5.5 V
TA = −40°C to +85°C
TA = −40°C to +125°C
1 mA
2 mA
ISB2 Standby Current
VIN = GND or VCC, CS = VCC,
WP = GND, VCC = 5.5 V
TA = −40°C to +85°C
TA = −40°C to +125°C
3 mA
5 mA
IL Input Leakage Current VIN = GND or VCC
−2 2 mA
ILO Output Leakage
Current
CS = VCC,
VOUT = GND or VCC
TA = −40°C to +85°C
TA = −40°C to +125°C
−1
−1
1 mA
2 mA
VIL Input Low Voltage
−0.5
0.3 VCC
V
VIH Input High Voltage
0.7 VCC
VCC + 0.5
V
VOL1 Output Low Voltage
VCC ≥ 2.5 V, IOL = 3.0 mA
0.4 V
VOH1 Output High Voltage
VCC ≥ 2.5 V, IOH = −1.6 mA
VCC − 0.8 V
V
VOL2 Output Low Voltage
VCC < 2.5 V, IOL = 150 mA
0.2 V
VOH2 Output High Voltage
VCC < 2.5 V, IOH = −100 mA
VCC − 0.2 V
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 4. PIN CAPACITANCE (Note 2) (TA = 25°C, f = 1.0 MHz, VCC = +5.0 V)
Symbol
Test
Conditions
COUT
CIN
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
VOUT = 0 V
VIN = 0 V
Min Typ Max Units
8 pF
8 pF
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CAT25320
Table 5. A.C. CHARACTERISTICS
(TA = −40°C to +85°C (Industrial) and TA = −40°C to +125°C (Extended).) (Notes 4, 7)
VCC = 1.8 V − 5.5 V / −405C to +855C
VCC = 2.5 V − 5.5 V / −405C to +1255C
Symbol
Parameter
Min Max
VCC = 2.5 V − 5.5 V
−405C to +855C
Min Max
Units
fSCK
Clock Frequency
DC 5
tSU Data Setup Time
40
tH Data Hold Time
40
tWH SCK High Time
75
tWL SCK Low Time
75
tLZ HOLD to Output Low Z
50
tRI (Note 5)
Input Rise Time
2
tFI (Note 5)
Input Fall Time
2
tHD HOLD Setup Time
0
tCD HOLD Hold Time
10
tV Output Valid from Clock Low
75
tHO Output Hold Time
0
tDIS Output Disable Time
50
tHZ HOLD to Output High Z
100
tCS CS High Time
50
tCSS
CS Setup Time
20
tCSH
CS Hold Time
30
tCNS
CS Inactive Setup Time
50
tCNH
CS Inactive Hold Time
50
tWPS
WP Setup Time
10
tWPH
WP Hold Time
100
tWC (Note 6)
Write Cycle Time
5
4. AC Test Conditions:
Input Pulse Voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤ 10 ns
Input and output reference voltages: 0.5 VCC
Output load: current source IOL max/IOH max; CL = 50 pF
5. This parameter is tested initially and after a design or process change that affects the parameter.
DC
20
20
40
40
0
10
0
20
15
20
15
15
10
60
10 MHz
ns
ns
ns
ns
25 ns
2 ms
2 ms
ns
ns
40 ns
ns
20 ns
25 ns
ns
ns
ns
ns
ns
ns
ns
5 ms
6. tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
7. All Chip Select (CS) timing parameters are defined relative to the positive clock edge (Figure 2). tCSH timing specification is valid
for die revision C and higher. The die revision C is identified by letter “C” or a dedicated marking code on top of the package. For
previous product revision (Rev. B) the tCSH is defined relative to the negative clock edge.
Table 6. POWER−UP TIMING (Notes 5, 8)
Symbol
Parameter
Max
tPUR
Power−up to Read Operation
1
tPUW
Power−up to Write Operation
1
8. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Units
ms
ms
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