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CAT93C46 PDF даташит

Спецификация CAT93C46 изготовлена ​​​​«ON Semiconductor» и имеет функцию, называемую «1Kb Microwire Serial EEPROM».

Детали детали

Номер произв CAT93C46
Описание 1Kb Microwire Serial EEPROM
Производители ON Semiconductor
логотип ON Semiconductor логотип 

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CAT93C46 Даташит, Описание, Даташиты
CAT93C46
1 Kb Microwire Serial
EEPROM
Description
The CAT93C46 is a 1 Kb Serial EEPROM memory device which is
configured as either 64 registers of 16 bits (ORG pin at VCC) or 128
registers of 8 bits (ORG pin at GND). Each register can be written (or
read) serially by using the DI (or DO) pin. The CAT93C46 features a
selftimed internal write with autoclear. Onchip PowerOn Reset
circuit protects the internal logic against powering up in the wrong
state.
Features
High Speed Operation: 2 MHz
1.8 V to 5.5 V Supply Voltage Range
Selectable x8 or x16 Memory Organization
SelfTimed Write Cycle with AutoClear
Software Write Protection
Powerup Inadvertant Write Protection
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial Temperature Range
8pin PDIP, SOIC, TSSOP and 8pad TDFN Packages
This Device is PbFree, Halogen Free/BFR Free and RoHS
Compliant*
VCC
ORG
CS
SK
DI
CAT93C46
DO
GND
Figure 1. Functional Symbol
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
PDIP8
L SUFFIX
CASE 646AA
TSSOP8
Y SUFFIX
CASE 948AL
SOIC8
V, W SUFFIX
CASE 751BD
SOIC8
X SUFFIX
CASE 751BE
TDFN8*
VP2 SUFFIX
CASE 511AK
PIN CONFIGURATIONS
CS 1
SK
DI
DO
VCC
NC
ORG
GND
NC
VCC
CS
SK
PDIP (L), SOIC (V, X),
TSSOP (Y), TDFN (VP2)*
(Top View)
1 ORG
GND
DO
DI
SOIC (W)
(Top View)
PIN FUNCTION
Pin Name
Function
CS Chip Select
SK Clock Input
DI Serial Data Input
DO Serial Data Output
VCC
GND
Power Supply
Ground
ORG
Memory Organization
NC No Connection
Note: When the ORG pin is connected to VCC, the
x16 organization is selected. When it is connected
to ground, the x8 organization is selected. If the
ORG pin is left unconnected, then an internal pullup
device will select the x16 organization.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
* Not Recommended for New Designs
© Semiconductor Components Industries, LLC, 2013
October, 2013 Rev. 10
1
Publication Order Number:
CAT93C46/D









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CAT93C46 Даташит, Описание, Даташиты
CAT93C46
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Value
Units
Storage Temperature
65 to +150
°C
Voltage on Any Pin with Respect to Ground (Note 1)
0.5 to +6.5
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than 0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than 1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
Parameter
Min Units
NEND (Note 3)
Endurance
1,000,000
Program / Erase Cycles
TDR Data Retention
100 Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100
and JEDEC test methods.
3. Block Mode, VCC = 5 V, 25°C
Table 3. D.C. OPERATING CHARACTERISTICS (VCC = +1.8 V to +5.5 V, TA = 40°C to +85°C, unless otherwise specified.)
Symbol
Parameter
Test Conditions Min Max Units
ICC1
ICC2
ISB1
Power Supply Current (Write)
Power Supply Current (Read)
Power Supply Current (Standby) (x8 Mode)
fSK = 1 MHz
VCC = 5.0 V
fSK = 1 MHz
VCC = 5.0 V
VIN = GND or VCC,
CS = GND
ORG = GND
1 mA
500 mA
2 mA
ISB2
Power Supply Current (Standby) (x16Mode)
VIN = GND or VCC,
CS = GND
ORG = Float or VCC
ILI Input Leakage Current
VIN = GND to VCC
ILO Output Leakage Current
VOUT = GND to VCC,
CS = GND
1 mA
1 mA
1 mA
VIL1
VIH1
VIL2
VIH2
VOL1
VOH1
VOL2
VOH2
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
4.5 V v VCC < 5.5 V
4.5 V v VCC < 5.5 V
1.8 V v VCC < 4.5 V
1.8 V v VCC < 4.5 V
4.5 V v VCC < 5.5 V
IOL = 2.1 mA
4.5 V v VCC < 5.5 V
IOH = 400 mA
1.8 V v VCC < 4.5 V
IOL = 1 mA
1.8 V v VCC < 4.5 V
IOH = 100 mA
0.1
2
0
VCC x 0.7
2.4
VCC 0.2
0.8
VCC + 1
VCC x 0.2
VCC + 1
0.4
0.2
V
V
V
V
V
V
V
V
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CAT93C46 Даташит, Описание, Даташиты
CAT93C46
Table 4. PIN CAPACITANCE (TA = 25°C, f = 1 MHz, VCC = 5 V)
Symbol
Test
Conditions
Min Typ Max Units
COUT (Note 4)
Output Capacitance (DO)
VOUT = 0 V
5 pF
CIN (Note 4)
Input Capacitance (CS, SK, DI, ORG)
VIN = 0 V
5 pF
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100
and JEDEC test methods.
Table 5. A.C. CHARACTERISTICS (VCC = +1.8 V to +5.5 V, TA = 40°C to +85°C, unless otherwise specified.) (Note 5)
Limits
Symbol
Parameter
Min Max Units
tCSS
CS Setup Time
50 ns
tCSH
CS Hold Time
0 ns
tDIS DI Setup Time
100 ns
tDIH DI Hold Time
100 ns
tPD1 Output Delay to 1
0.25 ms
tPD0 Output Delay to 0
0.25 ms
tHZ (Note 6)
Output Delay to HighZ
100 ns
tEW (Note 7)
Program/Erase Pulse Width
5 ms
tCSMIN
Minimum CS Low Time
0.25 ms
tSKHI
Minimum SK High Time
0.25 ms
tSKLOW
Minimum SK Low Time
0.25 ms
tSV Output Delay to Status Valid
0.25 ms
SKMAX
Maximum Clock Frequency
DC
2000
kHz
5. Test conditions according to “AC Test Conditions” table.
6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100
and JEDEC test methods.
7. tEW is 10 ms max for ERAL and WRAL operations.
Table 6. POWERUP TIMING (Notes 8 and 9)
Symbol
Parameter
Max Units
tPUR
Powerup to Read Operation
1 ms
tPUW
Powerup to Write Operation
1 ms
8. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100
and JEDEC test methods.
9. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Table 7. A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Output Load
v 50 ns
0.4 V to 2.4 V
4.5 V v VCC v 5.5 V
0.8 V, 2.0 V
0.2 VCC to 0.7 VCC
4.5 V v VCC v 5.5 V
1.8 V v VCC v 4.5 V
0.5 VCC
1.8 V v VCC v 4.5 V
Current Source IOLmax/IOHmax; CL = 100 pF
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