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Спецификация CAT34TS04 изготовлена «ON Semiconductor» и имеет функцию, называемую «Digital Output Temperature Sensor». |
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Детали детали
Номер произв | CAT34TS04 |
Описание | Digital Output Temperature Sensor |
Производители | ON Semiconductor |
логотип |
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CAT34TS04
Digital Output Temperature
Sensor with On-board SPD
EEPROM
Description
The CAT34TS04 is a combination Temperature Sensor (TS) and
4−Kb of Serial Presence Detect (SPD) EEPROM, which implements
the JEDEC TSE2004av DDR4 specification and supports the Standard
(100 kHz), Fast (400 kHz) and Fast Plus (1 MHz) I2C protocols.
The TS measures temperature at least 10 times every second.
Temperature readings can be retrieved by the host via the serial
interface, and are compared to high, low and critical trigger limits
stored into internal registers. Over or under limit conditions can be
signaled on the open−drain EVENT pin.
One of the two available 2−Kb SPD EEPROM banks (referred to as
SPD pages in the TSE2004av specification) is activated for access at
power−up. After power−up, banks can be switched via software
command. Each of the four 1−Kb SPD EEPROM blocks can be Write
Protected by software command.
Features
• JEDEC TSE2004av Compliant Temperature Sensor
• Temperature Range: −20°C to +125°C
• DDR4 DIMM Compliant SPD EEPROM
• Supply Range: 1.7 V − 5.5 V (SPD EEPROM) and
2.2 V − 5.5 V (TS)
• I2C / SMBus Interface
• Schmitt Triggers and Noise Suppression Filters on SCL and SDA
Inputs
• 16−Byte Page Write Buffer
• Low Power CMOS Technology
• 2 x 3 x 0.75 mm TDFN Package and 2 x 3 x 0.5 mm UDFN Package
• These Devices are Pb−Free and are RoHS Compliant
VCC
SCL
A2, A1, A0
SDA
CAT34TS04
EVENT
VSS
Figure 1. Functional Symbol
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TDFN−8
VP2 SUFFIX
CASE 511AK
UDFN−8
HU4 SUFFIX
CASE 517AZ
PIN CONFIGURATION
A0 1
A1
A2 (Top View)
VSS
VCC
EVENT
SCL
SDA
TDFN (VP2), UDFN (HU4)
For the location of Pin 1, please consult the
corresponding package drawing.
MARKING DIAGRAM
TDFN−8
4TA
ALL
YM
G
4UA
ALL
YM
UDFN−8
G
4TA, 4UA = Specific Device Code
A = Assembly Location Code
LL = Assembly Lot Number (Last Two Digits)
Y = Production Year (Last Digit)
M = Production Month (1 − 9, O, N, D)
G = Pb−Free Package
= Pin 1 Indicator
PIN FUNCTIONS
Pin Name
A0, A1, A2
SDA
SCL
EVENT
VCC
VSS
DAP
Function
Device Address Input
Serial Data Input/Output
Serial Clock Input
Open−drain Event Output
Power Supply
Ground
Backside Exposed DAP at VSS
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
October, 2013 − Rev. 6
1
Publication Order Number:
CAT34TS04/D
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CAT34TS04
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Units
Operating Temperature
−45 to +130
°C
Storage Temperature
−65 to +150
°C
Voltage on any pin (except A0) with respect to Ground (Note 1)
−0.5 to +6.5
V
Voltage on pin A0 with respect to Ground
−0.5 to +10.5
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. The A0 pin can be raised to a HV level for SWP
command execution. SCL and SDA inputs can be raised to the maximum limit, irrespective of VCC.
Table 2. RELIABILITY CHARACTERISTICS
Symbol
Parameter
NEND (Note 2)
Endurance (EEPROM)
TDR Data Retention (EEPROM)
2. Page Mode, VCC = 2.5 V, 25°C
Min
1,000,000
100
Units
Write Cycles
Years
Table 3. TEMPERATURE CHARACTERISTICS (VCC = 2.2 V to 3.6 V, TA = −20°C to +125°C, unless otherwise specified)
Parameter
Test Conditions/Comments
Max Unit
Temperature Reading Error
ADC Resolution
+75°C ≤ TA ≤ +95°C, active range
+40°C ≤ TA ≤ +125°C, monitor range
−20°C ≤ TA ≤ +125°C, sensing range
±1.0 °C
±2.0 °C
±3.0 °C
12 Bits
Temperature Resolution
0.0625
°C
Conversion Time
100 ms
Thermal Resistance (Note 3) qJA
Junction−to−Ambient (Still Air)
92 °C/W
3. Power Dissipation is defined as PJ = (TJ − TA)/qJA, where TJ is the junction temperature and TA is the ambient temperature. The thermal
resistance value refers to the case of a package being used on a standard 2−layer PCB.
Table 4. D.C. OPERATING CHARACTERISTICS (VCC = 2.2 V to 3.6 V, TA = −20°C to +125°C, unless otherwise specified)
Symbol
Parameter
Test Conditions/Comments Min Max Unit
ICC Supply Current
TS active, SPD and Bus idle
SPD Write, TS shut−down
1000
1000
mA
mA
ISHDN
Standby Current
TS shut−down; SPD and Bus idle
ILKG I/O Pin Leakage Current
Pin at GND or VCC
VIL Input Low Voltage
VIH Input High Voltage
VOL1 (Note 4)
Output Low Voltage
IOL = 3 mA, VCC > 2.2 V
VOL2
Output Low Voltage
IOL = 1 mA, VCC < 2.2 V
4. The device is able to handle RL values corresponding to the specified rise time (see Figure 2).
−0.5
0.7 x VCC
10
2
0.3 x VCC
VCC + 0.5
0.4
0.2
mA
mA
V
V
V
V
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CAT34TS04
Table 5. A.C. CHARACTERISTICS (VCC = 2.2 V to 3.6 V, TA = −20°C to +125°C)
Symbol
Parameter
Min
Max Units
FSCL (Note 5)
Clock Frequency
0.01 1 MHz
tHIGH
High Period of SCL Clock
260 ns
tLOW
Low Period of SCL Clock
500 ns
tTIMEOUT (Note 6)
SMBus SCL Clock Low Timeout
25 35 ms
tR (Note 7)
SDA and SCL Rise Time
120 ns
tF (Note 7)
SDA and SCL Fall Time
120 ns
tSU:DAT
Input Data Setup Time
50 ns
tSU:STA
START Condition Setup Time
260 ns
tHD:STA
START Condition Hold Time
260 ns
tSU:STO
STOP Condition Setup Time
260 ns
tBUF Bus Free Time Between STOP and START
500
ns
tHD:DAT
Input Data Hold Time
0 ns
tDH (Note 7)
Output Data Hold Time
120 300
ns
Ti Noise Pulse Filtered at SCL and SDA Inputs
50 ns
tWR Write Cycle Time
5 ms
tPU (Note 8)
Power-Up Delay to Valid Temperature Recording
100 ms
5. Timing reference points are set at 30%, respectively 70% of VCC, as illustrated in Figure 5. Bus loading must be such as to allow meeting
the VIL and VOL
operating clock
as well as all
frequency is
other timing
limited only
requirements. The minimum clock frequency of 10 kHz is an SMBus recommendation; the minimum
by the SMBus time−out. The device also meets the Fast and Standard I2C specifications, except
that Ti and tDH are shorter, as required by the 1 MHz Fast Plus protocol.
6. For the CAT34TS04, the interface will reset itself and will release the SDA line if the SCL line stays low beyond the tTIMEOUT limit. The time−out
count takes place when SCL is low in the time interval between START and STOP.
7. In a “Wired−OR” system (such as I2C or SMBus), SDA rise time is determined by bus loading. Since each bus pull−down device must be
able to sink the (external) bus pull−up current (in order to meet the VIL and/or VOL limits), it follows that SDA fall time is inherently faster than
SDA rise time. SDA rise time can exceed the standard recommended tR limit, as long as it does not exceed tLOW − tDH − tSU:DAT, where tLOW
and tDH are actual values (rather than spec limits). A shorter tDH leaves more room for a longer SDA tR, allowing for a more capacitive bus
or a larger bus pull−up resistor.
8. The first valid temperature recording can be expected after tPU at nominal supply voltage.
Table 6. PIN CAPACITANCE (TA = 25°C, VCC = 3.6 V, f = 1 MHz)
Symbol
Parameter
Test Conditions/Comments Min Max Unit
CIN SDA, EVENT Pin Capacitance
Input Capacitance (other pins)
VIN = 0
VIN = 0
8 pF
6 pF
10
300 ns Rise Time
120 ns Rise Time
1
SDA
0.1
10
100
LOAD CAPACITANCE (pF)
Figure 2. Pull−up Resistance vs. Load Capacitance
VCC
RL
CL
VSS
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