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74VHC08 PDF даташит

Спецификация 74VHC08 изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «Quad 2-input AND gate».

Детали детали

Номер произв 74VHC08
Описание Quad 2-input AND gate
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74VHC08 Даташит, Описание, Даташиты
74VHC08; 74VHCT08
Quad 2-input AND gate
Rev. 01 — 30 June 2009
Product data sheet
1. General description
The 74VHC08; 74VHCT08 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard JESD7-A.
The 74VHC08; 74VHCT08 provide the quad 2-input AND function.
2. Features
I Balanced propagation delays
I All inputs have a Schmitt-trigger action
I Inputs accepts voltages higher than VCC
I Input levels:
N The 74VHC08 operates with CMOS logic levels
N The 74VHCT08 operates with TTL logic levels
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
74VHC08D
74VHCT08D
40 °C to +125 °C SO14
plastic small outline package; 14 leads;
body width 3.9 mm
74VHC08PW
74VHCT08PW
40 °C to +125 °C
TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
74VHC08BQ
74VHCT08BQ
40 °C to +125 °C
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
Version
SOT108-1
SOT402-1
SOT762-1









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74VHC08 Даташит, Описание, Даташиты
NXP Semiconductors
4. Functional diagram
74VHC08; 74VHCT08
Quad 2-input AND gate
1 1A
2 1B
4 2A
5 2B
9 3A
10 3B
12 4A
13 4B
1Y 3
2Y 6
3Y 8
4Y 11
mna222
Fig 1. Logic symbol
1
&
2
3
4
&
5
6
9&
10
8
12 & 11
13
mna223
Fig 2. IEC logic symbol
5. Pinning information
5.1 Pinning
A
Y
B
mna221
Fig 3. Logic diagram (one gate)
74VHC08
74VHCT08
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 VCC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
001aak040
Fig 4. Pin configuration SO14 and TSSOP14
74VHC08
74VHCT08
terminal 1
index area
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND(1)
13 4B
12 4A
11 4Y
10 3B
9 3A
001aak041
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 5. Pin configuration DHVQFN14
74VHC_VHCT08_1
Product data sheet
Rev. 01 — 30 June 2009
© NXP B.V. 2009. All rights reserved.
2 of 14









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74VHC08 Даташит, Описание, Даташиты
NXP Semiconductors
74VHC08; 74VHCT08
Quad 2-input AND gate
5.2 Pin description
Table 2.
Symbol
1A
1B
1Y
2A
2B
2Y
GND
3Y
3A
3B
4Y
4A
4B
VCC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
data input
data input
data output
data input
data input
data output
ground (0 V)
data output
data input
data input
data output
data input
data input
supply voltage
6. Functional description
Table 3.
Input
nA
L
X
H
Function selection[1]
nB
X
L
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care
7. Limiting values
Output
nY
L
L
H
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC supply voltage
VI input voltage
IIK input clamping current
IOK output clamping current
IO output current
VI < 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to (VCC + 0.5 V)
0.5
0.5
[1] 20
[1] -
-
+7.0
+7.0
-
±20
±25
V
V
mA
mA
mA
ICC
IGND
Tstg
supply current
ground current
storage temperature
- 75 mA
75 -
mA
65 +150 °C
74VHC_VHCT08_1
Product data sheet
Rev. 01 — 30 June 2009
© NXP B.V. 2009. All rights reserved.
3 of 14










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