EDW2032BBBG PDF даташит
Спецификация EDW2032BBBG изготовлена «Elpida» и имеет функцию, называемую «2G bits GDDR5 SGRAM». |
|
Детали детали
Номер произв | EDW2032BBBG |
Описание | 2G bits GDDR5 SGRAM |
Производители | Elpida |
логотип |
17 Pages
No Preview Available ! |
DATA SHEET
2G bits GDDR5 SGRAM
EDW2032BBBG (64M words x 32 bits)
Specifications
Features
• Density: 2G bits
• Organization
— 4Mbit x 32 I/O x 16 banks
— 8Mbit x 16 I/O x 16 banks
• Package
— 170-ball FBGA
— Lead-free (RoHS compliant) and Halogen-free
• Power supply:
— VDD: 1.6V/1.5V ± 3% and 1.35V ± 3%
— VDDQ: 1.6V/1.5V ± 3% and 1.35V ± 3%
• Data rate: 7.0Gbps/6.0Gbps/5.0Gbps (max.)
• 16 internal banks
• Four bank groups for tCCDL = 3tCK
• 8n prefetch architecture: 256 bit per array Read or
Write access for x32; 128 bit for x16
• Burst length (BL): 8 only
• Programmable CAS latency: 6 to 20
• Programmable Write latency: 3 to 7
• Programmable CRC READ latency: 1 to 3
• Programmable CRC WRITE latency: 8 to 14
• Programmable EDC hold pattern for CDR
• Precharge: auto precharge option for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 16384 cycles/32ms
• Interface: Pseudo open drain (POD-15)
• On-die termination (ODT): nom. values of 60Ω or 120Ω
• Pseudo open drain (POD-15) compatible outputs
— 40Ω pulldown
— 60Ω pullup
• ODT and output driver strength auto-calibration with
external resistor ZQ pin (120Ω)
• Programmable termination and driver strength offsets
• Selectable external or internal VREF for data inputs;
programmable offsets for internal VREF
• Separate external VREF for address / command inputs
• Operating case temperature range
— TC = 0°C to +95°C
• x32/x16 mode configuration set at power-up with
EDC pin
• Single ended interface for data, address and command
• Quarter data-rate differential clock inputs CK, /CK for
address and commands
• Two half data-rate differential clock inputs WCK, /WCK,
each associated with two data bytes (DQ, /DBI, EDC)
• Double Data Rate (DDR) data (WCK)
• Single Data Rate (SDR) command (CK)
• Double Data Rate (DDR) addressing (CK)
• Write data mask function via address bus
(single/double byte mask)
• Data Bus Inversion (DBI) and Address Bus Inversion
(ABI)
• Input/output PLL on/off mode
• Duty cycle corrector (DCC) for data clock (WCK)
• Address training: address input monitoring via DQ pins
• WCK2CK clock training: phase information via EDC
pins
• Data read and write training via Read FIFO (FIFO
depth = 6)
• Read FIFO pattern preload by LDFF command
• Direct write data load to Read FIFO by WRTR
command
• Consecutive read of Read FIFO by RDTR command
• Read/Write data transmission integrity secured by
cyclic redundancy check (CRC–8)
• Read/Write EDC on/off mode
• DQ Preamble for Read on/off mode
• Low Power modes
• RDQS mode on EDC pin
• On-chip temperature sensor with read-out
• Automatic temperature sensor controlled self-refresh
rate
• Digital tRAS lockout
• Vendor ID, FIFO depth and Density info fields for
identification
• Mirror function with MF pin
• Boundary Scan function with SEN pin
Document No. E1864E10 (Ver. 1.0)
Date Published December 2011 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2011
No Preview Available ! |
Ordering Information
EDW2032BBBG
Part number
EDW2032BBBG-40-F
EDW2032BBBG-50-F
EDW2032BBBG-60-F
EDW2032BBBG-70-F
Organization
(words x bits)
64M x 32
VDD, VDDQ
1.5V / 1.35V
1.5V / 1.35V
1.6V / 1.35V
1.6V / 1.35V
Max. Data Rate
4.0Gbps / 3.2Gbps
5.0Gbps / 4.0Gbps
6.0Gbps / 4.0Gbps
7.0Gbps / 4.0Gbps
Package
170-ball FBGA
Part Number
E D W 20 32 B B BG - 60 - F
Elpida Memory
Type
D: Packaged Device
Product Family
W: GDDR5 SGRAM
Density/Bank
20: 2Gb/16-bank
Organization
32: x32
Power Supply, Interface
B: VDD = 1.5V
Environment Code
F: Lead Free (RoHS compliant)
and Halogen Free
Speed
40: 4.0Gbps
50: 5.0Gbps
60: 6.0Gbps
70: 7.0Gbps
Package
BG: FBGA
Revision
Data Sheet E1864E10 (Ver. 1.0)
2
No Preview Available ! |
Pin Configuration
EDW2032BBBG
EDOO )%*$ 0) &RQILJXUDWLRQ
9664 '4 9664 '4 1&
$ 95()' '4 9664 '4 9664
9''4 '4 9''4 '4 966 % 966 '4 9''4 '4 9''4
9664 ('& 9664 9664 9'' & 9'' 9664 9664 ('& 9664
9''4 '%, 9''4 :&. :&.
'
966 9'' 9''4 '%, 9''4
9664 '4 9664 '4 9''4 ( 9''4 '4 9664 '4 9664
9''4 '4 9''4 '4 9664 ) 9664 '4 9''4 '4 9''4
9'' 9''4 5$6 9'' 966 * 966 9'' &6 9''4 9''
966
9664 9''4
$
$
$
$
+
%$
$
%$
$
9''4 9664
966
0) 5(6(7 &.(
$%,
$
5)8
-
6(1 &. &. =4 95()&
966 9664 9''4
$
$
$
$
.
%$
$
%$
$
9''4 9664
966
9'' 9''4 &$6 9'' 966 / 966 9'' :( 9''4 9''
9''4 '4 9''4 '4 9664 0 9664 '4 9''4 '4 9''4
9664 '4 9664 '4 9''4 1 9''4 '4 9664 '4 9664
9''4 '%, 9''4 :&. :&.
3
966 9'' 9''4 '%, 9''4
9664 ('& 9664 9664 9'' 5 9'' 9664 9664 ('& 9664
9''4 '4 9''4 '4 966 7 966 '4 9''4 '4 9''4
9664 '4 9664 '4 1&
8 95()' '4 9664 '4 9664
SLQ LV 2)) LQ [ PRGH
7RS 9LHZ
Data Sheet E1864E10 (Ver. 1.0)
3
Скачать PDF:
[ EDW2032BBBG.PDF Даташит ]
Номер в каталоге | Описание | Производители |
EDW2032BBBG | 2G bits GDDR5 SGRAM | Elpida |
EDW2032BBBG | GDDR5 SGRAM | Micron |
Номер в каталоге | Описание | Производители |
TL431 | 100 мА, регулируемый прецизионный шунтирующий регулятор |
Unisonic Technologies |
IRF840 | 8 А, 500 В, N-канальный МОП-транзистор |
Vishay |
LM317 | Линейный стабилизатор напряжения, 1,5 А |
STMicroelectronics |
DataSheet26.com | 2020 | Контакты | Поиск |