NCP51510 PDF даташит
Спецификация NCP51510 изготовлена «ON Semiconductor» и имеет функцию, называемую «Termination Source / Sink Regulator». |
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Детали детали
Номер произв | NCP51510 |
Описание | Termination Source / Sink Regulator |
Производители | ON Semiconductor |
логотип |
7 Pages
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NCP51510, NCV51510
3 Amp VTT Termination
Source / Sink Regulator for
DDR, DDR-2, DDR-3, DDR-4
The NCP51510 is a source/sink Double Data Rate (DDR)
termination regulator specifically designed for low input voltage and
low−noise systems where space is a key consideration. The
NCP51510 maintains a fast transient response and only requires a
minimum VTT load capacitance of 10 mF for output stability. The
NCP51510 supports remote sensing and all power requirements for
DDR VTT bus termination. The NCP51510 can also be used in
low−power chipsets and graphics processor cores that require
dynamically adjustable output voltages. The NCP51510 is available in
the thermally−efficient DFN10 Exposed Pad package, and is rated
both Green and Pb−Free.
Features
• Generate DDR Memory Termination Voltage (VTT)
• For DDR, DDR−2, DDR−3 and DDR−4 Source / Sink Currents
• Supports Loads Up to ±3 A (Typ), Output is Over−Current Protected
• Integrated MOSFETs with Thermal Shutdown Protection
• Fast Load−Transient Response
• PGOOD Output Pin to Monitor Status of VTT Output Regulation
• SS Input Pin for Suspend Shutdown mode
• VRI Input Reference for Flexible Voltage Tracking
• VTTS Input for Remote Sensing (Kelvin Connection)
• Built−in Soft−Start, Under Voltage Lockout
• Small, Low−Profile 10−pin, 3 x 3 mm DFN Package
• NCV51510MWTAG − Wettable Flank Option for Enhanced Optical
Inspection
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable*
• This is a Pb−Free Device
Applications
• DDR Memory Termination
• Desktop PC’s, Notebooks, and Workstations
• Servers and Networking equipment
• Telecom/Datacom, GSM Base Station
• Graphics Processor Core Supplies
• Set Top Boxes, LCD−TV/PDP−TV, Copier/Printers
• Supplies Power for Chipset/RAM as Low as 0.5 V
• Active Source/Sink Bus Termination
www.onsemi.com
DFN10
CASE 485C
MARKING DIAGRAM
51510
ALYWG
G
51510 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
VRO 1
VCC 2
AGND 3
VRI 4
PGOOD 5
GND
(Top View)
10 PVCC
9 VTT
8 PGND
7 SS
6 VTTS
ORDERING INFORMATION
Device
Package Shipping†
NCP51510MNTAG
NCV51510MNTAG*
NCV51510MWTAG*
DFN10
(Pb−Free)
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
April, 2015 − Rev. 2
1
Publication Order Number:
NCP51510/D
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NCP51510, NCV51510
PIN FUNCTION DESCRIPTION
Pin Number Pin Name
Pin Function
1 VRO OUTPUT − Buffered Output of VRI Reference Input pin.
2 VCC INPUT − Regulator Analog Power Input pin. Connect to the system supply voltage. Bypass VCC to AGND
with a 1 mF or greater ceramic capacitor.
3
AGND
Analog Ground
4 VRI INPUT − External Reference Input for VTT Output (see Figure 1 for typical application)
5
PGOOD
OUTPUT − VTT “Power Good” pin (open drain output)
6
VTTS
INPUT − Remote Sense Input for VTT. The VTTS pin provides accurate remote feedback sensing of the
VTT output.
7 SS INPUT − Suspend Shutdown Control Input. CMOS compatible. Logic HIGH = enable,
logic LOW = shutdown. Connect to VDDQ for normal operation.
8
PGND
Power Ground. Internally connected to Low−side MOSFET
9 VTT OUTPUT − Regulated Power Output pin
10
PVCC
INPUT − Regulator Power Input pin. Internally connected to High−side MOSFET
− THERMAL Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple vias
PAD
for maximum power dissipation performance.
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
PVCC to PGND
(Note 1)
−
−0.3 to 4.3
VCC to AGND
(Note 1)
VCC
−0.3 to 4.3
VRI, VRO, SS, PGOOD to AGND
VTT to PGND
(Note 1) − −0.3 to (VCC + 0.3)
V
(Note 1) − −0.3 to (PVCC + 0.3)
VTTS to AGND
(Note 1)
VTTS
−0.3 to (PVCC + 0.3)
PGND to AGND
PGND
−0.3 to +0.3
Storage Temperature
Operating Junction Temperature Range
Tstg −65 to 150
°C
TJ −40 to 125
ESD Capability, Human Body Model
(Note 2)
ESDHBM
2000
V
ESD Capability, Machine Model
(Note 2)
ESDMM
200
V
VTT Output Continuous RMS Current
100 sec
1 sec
−
±1.6
A
±2.5
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
DISSIPATION RATINGS
Package
10−Pin DFN
TA =705C Power Rate
1951 mW
Derating Factor Above TA = 705C
24.4 mW / °C
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NCP51510, NCV51510
RECOMMENED OPERATING CONDITIONS
Rating
Symbol
Value
Unit
VTT Output Voltage Range
VTT, VTTS
0.5 to 1.5
PVCC Input Voltage Range (Power)
VCC Input Voltage Range (Analog)
PVCC
VCC
1.1 to 3.6
2.7 to 3.6
V
Logic Voltage Range
SS, PGOOD
0 to VCC
Operating Ambient Temperature Range
TA
−40 to +125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL CHARACTERISTICS
PVCC = 1.8 V; VCC = 3.3 V; VRI = VTTS = 1.25 V; SS = VCC; (circuit of Figure 1, −40°C ≤ (TJ = TA) ≤ 125°C; unless otherwise noted.
Typical values are at TA = +25°C
Parameter
Conditions
Symbol Min Typ Max Unit
OUTPUT
VTT Output Voltage Range
PVCC > (VTT + VDROPOUT)
VTT 0.5
1.5 V
VTT Load Regulation
−1 A ≤ ITT ≤ +1 A
DVLOAD
−4
+4 mV
VTT Line−Regulation
1.4 V ≤ PVCC ≤ 3.3 V, IOUT = ±100 mA
DVLINE
1
Feedback−Voltage Error
VRI to VTTS,
ITT = ±200 mA
TA = −40°C to 125°C
VTTS
−17
+17
VTT Current Slew Rate
COUT = 100 mF, ITT = 0.1 A to 2 A
ITT di/dt
3
A/ms
VTT Output Power−Supply Rejec-
10 Hz < f < 10 kHz, ITT = 200 mA,
PSRR
80
dB
tion Ratio
COUT = 100 mF
VTT Output MOSFET RDS(on)
High−side (source) (ITT = +100 mA)
RDS(on)
140 250 mW
Low−side (sink) (ITT = −100 mA)
140 250
VTT Output−to−VTTS Input
Internal Feedback Resistance
RFB
12 kW
Discharge MOSFET RDS(on)
SS = 0 V
RDIS 8 W
SUPPLY CURRENT
Quiescent PVCC Current
Quiescent VCC Current
Shutdown PVCC Current
Shutdown VCC Current
REFERENCE
No Load
VRI > 0.45 V, No Load
SS = 0 V
SS = 0V, VRI = 0 V
SS = 0V, VRI > 0.45 V
IPVCC
ICC
IPVCC SD
ICC SD
0.4 10 mA
0.7 1.3
0.1 10 mA
50 100
350 600
VRI Input Voltage Range
VRI Input−Bias current
VRO Output Voltage
TA = +25°C
VCC = 3.3 V, IRO = 0
VRI
IRI
VRO
0.5 1.5 V
−1 +1 mA
VRI VRI VRI mV
−10 +10
VRO Load Regulation
SUSPEND SHUTDOWN
IRO = ±5 mA
DVRO
−20
+20
SS − Suspend Shutdown Logic
Input Threshold
SS Logic HI (VTT Output Enabled)
SS Logic LOW (VTT Suspended)
SS − Logic Input Current
SS = VCC or 0 V, TA = +25°C
FAULT CONDITION − CURRENT LIMIT
VIH 2.0
VIL
ISS −1
V
0.8
+1 mA
Current−Limit Threshold
Soft−start Current−limit time
TA = −40°C to +125°C
ITT LIMIT
1.8
3
4.2
TSS 200
A
ms
www.onsemi.com
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