SESD9L PDF даташит
Спецификация SESD9L изготовлена «ON Semiconductor» и имеет функцию, называемую «TVS Diode ( Rectifier )». |
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Детали детали
Номер произв | SESD9L |
Описание | TVS Diode ( Rectifier ) |
Производители | ON Semiconductor |
логотип |
4 Pages
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ESD9L, SESD9L Series
Transient Voltage
Suppressors
ESD Protection Diodes with Ultra−Low
Capacitance
The ESD9L Series is designed to protect voltage sensitive components
that require ultra−low capacitance from ESD and transient voltage
events. Excellent clamping capability, low capacitance, low leakage, and
fast response time, make these parts ideal for ESD protection on designs
where board space is at a premium. Because of its low capacitance, it is
suited for use in high frequency designs such as USB 2.0 high speed and
antenna line applications.
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PIN 1. CATHODE
2. ANODE
Specification Features:
• Ultra Low Capacitance 0.5 pF
• Low Clamping Voltage
• Small Body Outline Dimensions:
0.039″ x 0.024″ (1.00 mm x 0.60 mm)
• Low Body Height: 0.016″ (0.4 mm)
• Stand−off Voltage: 3.3 V, 5 V
• Low Leakage
• Response Time is Typically < 1.0 ns
• IEC61000−4−2 Level 4 ESD Protection
• S Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
• This is a Pb−Free Device
Mechanical Characteristics:
CASE: Void-free, transfer-molded, thermosetting plastic
Epoxy Meets UL 94 V−0
LEAD FINISH: 100% Matte Sn (Tin)
MOUNTING POSITION: Any
QUALIFIED MAX REFLOW TEMPERATURE: 260°C
Device Meets MSL 1 Requirements
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
IEC 61000−4−2 (ESD)
Contact
Air
±10 kV
±15
Total Power Dissipation on FR−5 Board
(Note 1) @ TA = 25°C
Storage Temperature Range
Junction Temperature Range
Lead Solder Temperature − Maximum
(10 Second Duration)
°PD°
Tstg
TJ
TL
150 mW
−55 to +150
−55 to +150
260
°C
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR−5 = 1.0 x 0.75 x 0.62 in.
2
1
SOD−923
CASE 514AB
MARKING DIAGRAM
1 XM 2
X = Specific Device Code
M = Date Code
*Date Code orientation and/or position may
vary depending upon manufacturing location.
ORDERING INFORMATION
Device
Package
Shipping†
ESD9LxxxST5G SOD−923 8000/Tape & Reel
(Pb−Free)
SESD9LxxxST5G SOD−923 8000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
DEVICE MARKING INFORMATION
See specific marking information in the device marking
column of the Electrical Characteristics tables starting on
page 2 of this data sheet.
See Application Note AND8308/D for further description of survivability specs.
© Semiconductor Components Industries, LLC, 2012
October, 2012 − Rev. 5
1
Publication Order Number:
ESD9L/D
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ESD9L, SESD9L Series
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Symbol
Parameter
IPP Maximum Reverse Peak Pulse Current
VC Clamping Voltage @ IPP
VRWM Working Peak Reverse Voltage
IR Maximum Reverse Leakage Current @ VRWM
VBR Breakdown Voltage @ IT
IT Test Current
IF Forward Current
VF Forward Voltage @ IF
Ppk Peak Power Dissipation
C Max. Capacitance @ VR = 0 and f = 1.0 MHz
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
I
IF
VC VBR VRWM
IIRT VF
IPP
Uni−Directional TVS
V
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted, VF = 1.0 V Max. @ IF = 10 mA for all types)
VRWM
(V)
IR (mA)
@ VRWM
VBR (V) @ IT
(Note 2)
IT
C (pF)
VC (V)
@ IPP = 1 A
VC
Device*
Device
Marking
Max
Max
Per IEC61000−4−2
Min
mA Typ Max
Max
(Note 4)
ESD9L3.3ST5G
6**
3.3
1.0
4.8 1.0 0.5 0.9 9.0
Figures 1 and 2
See Below
ESD9L5.0ST5G
D
5.0
1.0
5.4 1.0 0.5 0.9 9.8
Figures 1 and 2
See Below
* Include S-prefix devices where applicable.
**Rotated 180°.
2. VBR is measured with a pulse test current IT at an ambient temperature of 25°C.
3. Surge current waveform per Figure 5.
4. For test procedure see Figures 3 and 4 and Application Note AND8307/D.
Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2
Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV Contact per IEC61000−4−2
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ESD9L, SESD9L Series
IEC 61000−4−2 Spec.
Level
Test
Voltage
(kV)
First Peak
Current Current at
(A) 30 ns (A)
1 2 7.5 4
2 4 15 8
3 6 22.5 12
48
30 16
Current at
60 ns (A)
2
4
6
8
IEC61000−4−2 Waveform
Ipeak
100%
90%
I @ 30 ns
I @ 60 ns
10%
Figure 3. IEC61000−4−2 Spec
tP = 0.7 ns to 1 ns
ESD Gun
TVS
Oscilloscope
50 W
Cable
50 W
Figure 4. Diagram of ESD Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
100
90 tr
80
70
60
50
40
30
20
10
0
0
PEAK VALUE IRSM @ 8 ms
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
HALF VALUE IRSM/2 @ 20 ms
tP
20 40 60
t, TIME (ms)
Figure 5. 8 X 20 ms Pulse Waveform
80
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