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PDF HD6433037VF Data sheet ( Hoja de datos )
| Número de pieza | HD6433037VF | |
| Descripción | Single-Chip Microcomputer | |
| Fabricantes | Hitachi | |
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Hitachi Single-Chip Microcomputer
H8/3039 Series
H8/3039, H8/3038
H8/3037, H8/3036
H8/3039 F-ZTATTM
Hardware Manual
ADE-602-131A
Rev. 2.0
1/12/98
Hitachi,Ltd
1 page  
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ............................................. 86
5.2.3 IRQ Status Register (ISR) .................................................................................... 91
5.2.4 IRQ Enable Register (IER) .................................................................................. 92
5.2.5 IRQ Sense Control Register (ISCR)..................................................................... 93
5.3 Interrupt Sources................................................................................................................ 94
5.3.1 External Interrupts................................................................................................ 94
5.3.2 Internal Interrupts ................................................................................................. 95
5.3.3 Interrupt Vector Table .......................................................................................... 95
5.4 Interrupt Operation ............................................................................................................ 98
5.4.1 Interrupt Handling Process ................................................................................... 98
5.4.2 Interrupt Sequence................................................................................................ 103
5.4.3 Interrupt Response Time ...................................................................................... 104
5.5 Usage Notes ....................................................................................................................... 105
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction...................... 105
5.5.2 Instructions that Inhibit Interrupts........................................................................ 106
5.5.3 Interrupts during EEPMOV Instruction Execution .............................................. 106
5.5.4 Usage Notes.......................................................................................................... 106
Section 6 Bus Controller ................................................................................................ 109
6.1 Overview............................................................................................................................ 109
6.1.1 Features ................................................................................................................ 109
6.1.2 Block Diagram...................................................................................................... 110
6.1.3 Input/Output Pins.................................................................................................. 111
6.1.4 Register Configuration ......................................................................................... 111
6.2 Register Descriptions......................................................................................................... 112
6.2.1 Access State Control Register (ASTCR).............................................................. 112
6.2.2 Wait Control Register (WCR).............................................................................. 113
6.2.3 Wait State Controller Enable Register (WCER) .................................................. 114
6.2.4 Address Control Register (ADRCR).................................................................... 115
6.3 Operation ........................................................................................................................... 117
6.3.1 Area Division........................................................................................................ 117
6.3.2 Bus Control Signal Timing .................................................................................. 119
6.3.3 Wait Modes .......................................................................................................... 121
6.3.4 Interconnections with Memory (Example) .......................................................... 127
6.4 Usage Notes ....................................................................................................................... 129
6.4.1 Register Write Timing.......................................................................................... 129
6.4.2 Precautions on setting ASTCR and ABWCR* .................................................... 129
Section 7 I/O Ports ........................................................................................................... 131
7.1 Overview............................................................................................................................ 131
7.2 Port 1.................................................................................................................................. 135
7.2.1 Overview .............................................................................................................. 135
7.2.2 Register Descriptions............................................................................................ 135
iii
5 Page 
15.6.4 NMI Input Disable Conditions ............................................................................. 469
15.7 Flash Memory Emulation by RAM ................................................................................... 470
15.8 Flash Memory PROM Mode ............................................................................................. 471
15.8.1 PROM Mode Setting............................................................................................ 471
15.8.2 Memory Map........................................................................................................ 471
15.8.3 PROM Mode Operation ....................................................................................... 472
15.8.4 Memory Read Mode............................................................................................. 474
15.8.5 Auto-Program Mode ............................................................................................ 477
15.8.6 Auto-Erase Mode.................................................................................................. 479
15.8.7 Status Read Mode................................................................................................. 481
15.8.8 PROM Mode Transition Time.............................................................................. 482
15.8.9 Notes On Memory Programming ......................................................................... 483
15.9 Notes on Flash Memory Programming/Erasing................................................................ 484
15.10 Mask ROM Overview........................................................................................................ 489
15.10.1 Block Diagram...................................................................................................... 489
15.11 Notes on Ordering Mask ROM Version Chip .................................................................. 490
Section 16 Clock Pulse Generator .................................................................................. 491
16.1 Overview............................................................................................................................ 491
16.1.1 Block Diagram...................................................................................................... 492
16.2 Oscillator Circuit ............................................................................................................... 493
16.2.1 Connecting a Crystal Resonator ........................................................................... 493
16.2.2 External Clock Input ............................................................................................ 495
16.3 Duty Adjustment Circuit.................................................................................................... 498
16.4 Prescalers ........................................................................................................................... 498
16.5 Frequency Divider ............................................................................................................. 498
16.5.1 Register Configuration ......................................................................................... 498
16.5.2 Division Control Register (DIVCR) .................................................................... 499
16.5.3 Usage Notes.......................................................................................................... 499
Section 17 Power-Down State.......................................................................................... 501
17.1 Overview............................................................................................................................ 501
17.2 Register Configuration ...................................................................................................... 503
17.2.1 System Control Register (SYSCR) ...................................................................... 503
17.2.2 Module Standby Control Register (MSTCR)....................................................... 505
17.3 Sleep Mode........................................................................................................................ 507
17.3.1 Transition to Sleep Mode ..................................................................................... 507
17.3.2 Exit from Sleep Mode .......................................................................................... 507
17.4 Software Standby Mode .................................................................................................... 508
17.4.1 Transition to Software Standby Mode.................................................................. 508
17.4.2 Exit from Software Standby Mode....................................................................... 508
17.4.3 Selection of Oscillator Waiting Time after Exit from Software Standby Mode .. 509
17.4.4 Sample Application of Software Standby Mode.................................................. 510
ix
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