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PDF 74LVX373 Data sheet ( Hoja de datos )
| Número de pieza | 74LVX373 | |
| Descripción | LOW VOLTAGE CMOS OCTAL D-TYPE LATCH | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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74LVX373
LOW VOLTAGE CMOS OCTAL D-TYPE LATCH
(3-STATE NON INV.) WITH 5V TOLERANT INPUTS
s HIGH SPEED:
tPD=5.8ns (TYP.) at VCC = 3.3V
s 5V TOLERANT INPUTS
s POWER-DOWN PROTECTION ON INPUTS
s INPUT VOLTAGE LEVEL:
)VIL = 0.8V, VIH = 2V at VCC =3V
t(ss LOW POWER DISSIPATION:
cICC = 4 µA (MAX.) at TA=25°C
us LOW NOISE:
dVOLP = 0.3V (TYP.) at VCC =3.3V
ros SYMMETRICAL OUTPUT IMPEDANCE:
P|IOH| = IOL = 4 mA (MIN) at VCC =3V
s BALANCED PROPAGATION DELAYS:
tetPLH ≅ tPHL
les OPERATING VOLTAGE RANGE:
oVCC(OPR) = 2V to 3.6V (1.2V Data Retention)
bss PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
- Os IMPROVED LATCH-UP IMMUNITY
t(s)DESCRIPTION
The 74LVX373 is a low voltage CMOS OCTAL
cD-TYPE LATCH with 3 STATE OUTPUT NON
duINVERTING fabricated with sub-micron silicon
rogate and double-layer metal wiring C2MOS
technology. It is ideal for low power, battery
Poperated and low noise 3.3V applications.
teThis 8 bit D-Type latch is controlled by a latch
leenable input (LE) and an output enable input (OE).
oWhile the LE input is held at a high level, the Q
soutputs will follow the data input precisely.
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVX373MTR
74LVX373TTR
When the LE is taken low, the Q outputs will be
latched precisely at the logic level of D input data.
While the (OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V. It
combines high speed performance with the true
CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
ObFigure 1: Pin Connection And IEC Logic Symbols
August 2004
Rev. 4
1/13
1 page  
74LVX373
Table 9: Capacitive Characteristics
Test Condition
Value
Symbol
Parameter
VCC
(V)
TA = 25°C
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
CIN Input Capacitance 3.3
5 10 10 pF
COUT Output
Capacitance
3.3
10
pF
CPD Power Dissipation
Capacitance
3.3 fIN = 10MHz
40
pF
(note 1)
)1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per circuit)
t(sFigure 4: Test Circuit
te Product(s) - Obsolete ProductPLH,tPHL
letPZL, tPLZ
otPZH, tPHZ
TEST
bsCL =15/50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 1KΩ or equivalent
ORT = ZOUT of pulse generator (typically 50Ω)
SWITCH
Open
VCC
GND
5/13
5 Page 
74LVX373
Tape & Reel TSSOP20 MECHANICAL DATA
DIM.
MIN.
mm.
TYP
MAX.
MIN.
inch
TYP.
MAX.
A 330 12.992
C 12.8
13.2 0.504
0.519
D 20.2
0.795
N 60
t(s)T
cAo 6.8
duBo 6.9
roKo 1.7
PPo 3.9
Obsolete Product(s) - ObsoleteP 11.9
2.362
22.4
7 0.268
7.1 0.272
1.9 0.067
4.1 0.153
12.1 0.468
0.882
0.276
0.280
0.075
0.161
0.476
11/13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet 74LVX373.PDF ] | |
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