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PDF NB3N3020 Data sheet ( Hoja de datos )
| Número de pieza | NB3N3020 | |
| Descripción | LVPECL/LVCMOS Clock Multiplier | |
| Fabricantes | ON Semiconductor | |
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NB3N3020
3.3 V, LVPECL/LVCMOS
Clock Multiplier
Description
The NB3N3020 is a high precision, low phase noise selectable clock
multiplier. The device takes a 5 – 27 MHz fundamental mode parallel
resonant crystal or a 2 − 210 MHz LVCMOS single ended clock source
and generates a differential LVPECL output and a single ended
LVCMOS/LVTTL output at a selectable clock output frequency which
is a multiple of the input clock frequency. Three tri−level (Low, Mid,
High) LVCMOS/LVTTL single ended select pins set one of 26
possible clock multipliers. The LVCMOS/LVTTL output enable
(OE1) tri−states the LVCMOS/LVTTL clock output (CLK1) when
low. When the LVTTL/LVCMOS output enable (OE2) is LOW,
LVPECL CLK2 is forced LOW and LVPECL CLK2 is forced HIGH.
This device is housed in 5 mm x 4.4 mm narrow body TSSOP 16 pin
package.
Features
• Selectable Clock Multiplier
• External Loop Filter is Not Required
• LVPECL Differential Output
• LVCMOS/ LVTTL Outputs
• RMS Period Jitter of 5 ps
• Jitter or Low Phase Noise at 125 MHz [25 MHz Input]:
Offset
Noise Power
100 Hz
−95 dBc/Hz
1 kHz
−107 dBc/Hz
10 kHz
−112 dBc/Hz
100 kHz
−117 dBc/Hz
1 MHz
−117 dBc/Hz
10 MHz
−134 dBc/Hz
• Operating Range 3.3 V ±10%
• Industrial Temperature Range −40°C to +85°C
• These are Pb−Free Devices
http://onsemi.com
16
1
TSSOP−16
DT SUFFIX
CASE 948F
MARKING
DIAGRAM
16
NB3N
3020
ALYWG
1G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(*Note: Microdot may be in either location)
VDD
X1/CLK
X2
Sel2
Sel1
Sel0
OE1
GND
PIN CONFIGURATION
1 16
(Top View)
OE2
VDD
CLK2
CLK2
GND
VDD
CLK1
GND
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
January, 2014 − Rev. 4
1
Publication Order Number:
NB3N3020/D
1 page  
NB3N3020
Table 3. ATTRIBUTES
Characteristics
ESD Protection
Human Body Model
Moisture Sensitivity, Indefinite Time Out of Dry pack (Note 1)
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Value
2 kV
Level 1
UL 94 V−0 @ 0.125 in
8287 Devices
Table 4. MAXIMUM RATINGS (Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VDD Positive Power Supply
VI Input Voltage (VIN)
Iout LVPECL Output Current
GND = 0 V
GND = 0 V
Continuous
Surge
GND ≤ VI ≤ VDD
4.6
−0.5 V to VDD + 0.5 V
25
50
V
V
mA
TA Operating Temperature Range
Tstg Storage Temperature Range
qJA Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
TSSOP–16
TSSOP–16
−40 to +85
−65 to +150
138
108
°C
°C
°C/W
qJC Thermal Resistance (Junction−to−Case)
(Note 3)
TSSOP−16
33 to 36
°C/W
Tsol Wave Solder
265 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If
stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
Table 5. DC CHARACTERISTICS (VDD = 3.3 V ±10%, GND = 0 V, TA = −40°C to +85°C)
Symbol
Characteristic
Min Typ Max Unit
VDD
IDD
IDDOE
IDDOFF
VIH
VIL
VIH
VIL
VIM
VOH
VOL
VOH
VOL
Power Supply Voltage
Power Supply Current (Note 4)
Power Supply Current when OE1, OE2 is Set Low
Power Supply Current when PLL is powered off by Sel0, Sel1, Sel2
Input HIGH Voltage (X1/CLK, OE1, OE2)
Input LOW Voltage (X1/CLK, OE1, OE2)
Input HIGH Voltage (Sel0, Sel1, Sel2)
Input LOW Voltage (Sel0, Sel1, Sel2)
Input Mid Voltage (Sel0, Sel1, Sel2) (When left open, defaults to VDD/2
Output HIGH Voltage for CLK2, CLK2 (See Figure 3)
Output LOW Voltage for CLK2, CLK2 (See Figure 3)
Output HIGH Voltage for CLK1 [IOH = −12 mA]
Output LOW Voltage for CLK1 [IOL = 12 mA]
2.97 3.3
60
50
2000
GND − 300
0.72 VDD
GND − 300
VDD – 1.145
VDD – 2.090
2.4
VDD/2
3.63
75
5
VDD + 300
800
VDD + 300
800
VDD – 0.895
VDD – 1.600
0.4
V
mA
mA
mA
mV
mV
mV
mV
mV
V
V
V
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measurement taken at FCLKout = 125 MHz with LVPECL and LVCMOS/ LVTTL outputs not terminated.
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| PDF Descargar | [ Datasheet NB3N3020.PDF ] | |
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