PDF NB3N2302 Data sheet ( Hoja de datos )

Número de pieza	NB3N2302
Descripción	3.3V / 5V 5MHz to 133MHz Frequency Multiplier and Zero Delay Buffer
Fabricantes	ON Semiconductor
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No Preview Available ! NB3N2302 3.3V / 5V 5MHz to 133MHz Frequency Multiplier and Zero Delay Buffer Description The NB3N2302 is a versatile Zero Delay Buffer that operates from 5 MHz to 133 MHz with a 3.3 V or 5 V power supply. It accepts a reference input and drives a B1 and a B2 clock output. The NB3N2302 has an on−chip PLL which locks to the input reference clock presented on the REF_IN pin. The PLL feedback is required to be driven to the FBIN pin and can be obtained by connecting either the OUT1 or OUT2 pin to the FBIN pin. The Function Select inputs control the various multiplier output frequency combinations as shown in Table 1. Features • Output Frequency Range: 5 MHz to 133 MHz • Two LVTTL/LVCMOS Outputs • 65 ps Typical Jitter OUT2 • 115 ps Typical Jitter OUT1 • 25 ps Typical Output−to−Output Skew • Operating Voltage Range: VDD = 3.3 V $5% or 5 V $10% • Clock Multiplication of the Reference Input Frequency, See Table 1 for Options • Packaged in 8−Pin SOIC • −40°C to +85°C Ambient Operating Temperature Range • Ideal for PCI−X and Networking Clocks • These are Pb−Free Devices http://onsemi.com 8 1 SOIC−8 D SUFFIX CASE 751 2302 A L Y W G MARKING DIAGRAM 8 3N2302 ALYWG G 1 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. External feedback connection to OUT1 or OUT2, not both FS0 FS1 REF_IN FBIN Select Input Decoding PLL ÷2 OUT1 OUT2 Figure 1. Simplified Logic Diagram © Semiconductor Components Industries, LLC, 2011 October, 2011 − Rev. 1 1 Publication Order Number: NB3N2302/D 1 page NB3N2302 Overview The NB3N2302 is a two−output zero delay buffer and frequency multiplier. It provides an external feedback path allowing maximum flexibility when implementing the Zero Delay feature. This is explained further in the sections of this datasheet titled “How to Implement Zero Delay,” and “Inserting Other Devices in Feedback Path.” Figure 3. Schematic / Suggested Layout How to Implement Zero Delay Typically, Zero Delay Buffers (ZDBs) are used because a designer wants to provide multiple copies of a clock signal in phase with each other. The whole concept behind ZDBs is that the signals at the destination chips are all going HIGH at the same time as the input to the ZDB. In order to achieve this, layout must compensate for trace length between the ZDB and the target devices. The method of compensation is described as follows. External feedback is the trait that allows for this compensation. The PLL on the ZDB causes the feedback signal to be in phase with the reference signal. When laying out the board, match the trace lengths between the output being used for feedback and the FBIN input to the PLL. If it is desirable to either add a little delay, or slightly precede the input signal, this may also be implemented by either making the trace to the FBIN pin a little shorter or a little longer than the traces to the devices being clocked. Inserting Other Devices in Feedback Path Another nice feature available due to the external feedback is the ability to synchronize signals to the signal coming from some other device. This implementation can be applied to any device (ASIC, multiple output clock buffer/driver, etc.) that is put into the feedback path. Referring to Figure 4, if the traces between the ASIC/Buffer and the destination of the clock signal(s) are equal in length to the trace between the buffer and the FBIN pin, the signals at the destination(s) device is driven HIGH at the same time when the Reference clock provided to the ZDB goes HIGH. Synchronizing the other outputs of the ZDB to the outputs from the ASIC/Buffer is more complex however, as any propagation delay from the ZDB output to the ASIC/Buffer output must be accounted for. Reference Input Signal Feedback Signal NB3N2302 Zero Delay Buffer ASIC / Buffer / Fanout Figure 4. Output Buffer in the Feedback Path http://onsemi.com 5 5 Page

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