NB6L14S Datasheet PDF - ON Semiconductor
| Part Number | NB6L14S | |
| Description | 2.5V 1:4 AnyLevel Differential Input to LVDS Fanout Buffer/Translator | |
| Manufacturers | ON Semiconductor | |
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NB6L14S
2.5 V 1:4 AnyLevel]
Differential Input to LVDS
Fanout Buffer/Translator
The NB6L14S is a differential 1:4 Clock or Data Receiver and will
accept AnyLevel differential input signals: LVPECL, CML, LVDS, or
HSCL. These signals will be translated to LVDS and four identical
copies of Clock or Data will be distributed, operating up to 2.0 GHz or
2.5 Gb/s, respectively. As such, the NB6L14S is ideal for SONET,
GigE, Fiber Channel, Backplane and other Clock or Data distribution
applications.
The NB6L14S has a wide input common mode range from
GND + 50 mV to VCC − 50 mV. Combined with the 50 W internal
termination resistors at the inputs, the NB6L14S is ideal for translating
a variety of differential or single−ended Clock or Data signals to
350 mV typical LVDS output levels.
The NB6L14S is the 2.5 V version of the NB6N14S and is offered in
a small 3 mm x 3 mm 16−QFN package. Application notes, models,
and support documentation are available at www.onsemi.com.
The NB6L14S is a member of the ECLinPS MAX™ family of high
performance products.
Features
• Maximum Input Clock Frequency > 2.0 GHz
• Maximum Input Data Rate > 2.5 Gb/s
• 1 ps Maximum of RMS Clock Jitter
• Typically 10 ps of Data Dependent Jitter
• 380 ps Typical Propagation Delay
• 120 ps Typical Rise and Fall Times
• Single Power Supply; VCC = 2.5 $ 5%
• VREF_AC Reference Output
• These are Pb−Free Devices
Device DDJ = 10 ps
http://onsemi.com
1
QFN−16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB6L
14S
ALYW G
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q0
Q0
IN
VT
IN
50 W
50 W
EN
(LVTTL/CMOS)
VREFAC
DQ
Q1
Q1
Q2
Q2
Q3
Q3
Figure 1. Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 223−1 (VINPP = 400 mV; Input Signal DDJ = 14 ps)
© Semiconductor Components Industries, LLC, 2011
October, 2011 − Rev. 2
1
Publication Order Number:
NB6L14S/D
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NB6L14S
Table 6. AC CHARACTERISTICS VCC = 2.375 V to 2.625 V, GND = 0 V; (Note 12)
Symbol
finMax
VOUTPP
Characteristic
Maximum Input Clock Frequency
Output Voltage
(Figure 4)
Amplitude
(@
VINPPmin)
fDATA
tPLH,
tPHL
ts
th
tSKEW
Maximum Operating Data Rate
Differential Input to Differential Output, IN to Q
Propagation Delay @ 100 MHz
Setup Time
Hold Time
Within Device Skew (Note 17)
Device−to−Device Skew (Note 16)
ffinin=≤
1.0
1.5
GHz
GHz
fin= 2.0 GHz
EN to IN/IN
−40°C to +85°C
Min Typ Max
2.0
220 350
200 300
170 270
2.5
300 450 600
300 20
500 20
5 20
30 200
Unit
GHz
mV
Gb/s
ps
ps
tJITTER
VINPP
RMS Random Clock Jitter (Note 14)
Deterministic Jitter (Note 15)
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 13)
fDATA
vfin2=.428.80
GHz
Gb/s
0.5 0.8 ps
5.0 20
100 VCC−GND mV
tr Output Rise/Fall Times @ 250 MHz
tf (20% − 80%)
Q, Q
70 150 225 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
12. Measured by forcing VINPPmin with 50% duty cycle clock source and VCC − 1400 mV offset. All loading with an external RL = 100 W. Input
edge rates 150 ps (20%−80%). See Figure 20.
13. Input voltage swing is a single−ended measurement operating in differential mode.
14. RMS jitter with 50% Duty Cycle clock signal at 750 MHz.
15. Deterministic jitter with input NRZ data at PRBS 223−1 and K28.5.
16. Skew is measured between outputs under identical transition @ 250 MHz.
17. The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition.
400
350
300
250
200
150
100
50
0
0 0.5 1 1.5 2 2.5 3
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fin) and Temperature (@ VCC = 2.5 V)
http://onsemi.com
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| Information | Total 11 Pages | |
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