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PDF NLSV1T240 Data sheet ( Hoja de datos )

Número de pieza NLSV1T240
Descripción 1-Bit Dual-Supply Inverting Level Translator
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No Preview Available ! NLSV1T240 Hoja de datos, Descripción, Manual

NLSV1T240
1-Bit Dual-Supply Inverting
Level Translator
The NLSV1T240 is a 1bit configurable dualsupply voltage level
translator. The input An and output Bn ports are designed to track two
different power supply rails, VCCA and VCCB respectively. Both
supply rails are configurable from 0.9 V to 4.5 V allowing universal
lowvoltage translation from the input An to the output Bn port.
Features
Wide VCCA and VCCB Operating Range: 0.9 V to 4.5 V
HighSpeed w/ Balanced Propagation Delay
Inputs and Outputs have OVT Protection to 4.5 V
Nonpreferential VCCA and VCCB Sequencing
Outputs at 3State until Active VCC is Reached
PowerOff Protection
Outputs Switch to 3State with VCCB at GND
UltraSmall Packaging: 1.2 mm x 1.0 mm UDFN6
This is a PbFree Device
Typical Applications
Mobile Phones, PDAs, Other Portable Devices
Important Information
ESD Protection for All Pins:
Human Body Model (HBM) > 2000 V
VCCA
VCCB
AB
OE
Figure 1. Logic Diagram
http://onsemi.com
MARKING
DIAGRAM
1
UDFN6
MU SUFFIX
CASE 517AA
3M
G
3 = Specific Device Code
M = Date Code
G = PbFree Package
PIN ASSIGNMENT
VCCA 1
A2
GND 3
6 VCCB
5B
4 OE
(Top View)
ORDERING INFORMATION
Device
Package
Shipping
NLSV1T240MUTBG UDFN6 3000/Tape & Reel
(PbFree)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2012
February, 2012 Rev. 4
1
Publication Order Number:
NLSV1T240/D

1 page




NLSV1T240 pdf
Pulse
Generator
NLSV1T240
VCC
DUT
RL
CL RL
VCCO x 2
OPEN
GND
Figure 2. AC (Propagation Delay) Test Circuit
Test Switch
tPLH, tPHL
OPEN
tPLZ, tPZL
VCCO x 2
tPHZ, tPZH
GND
CL = 15 pF or equivalent (includes probe and jig capacitance)
RL = 2 kW or equivalent
ZOUT of pulse generator = 50 W
Input (A)
Output (B)
Vm
tPLH
Vm
Vm
tPHL
Vm
Waveform 1 Propagation Delays
tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
VIH
0V
VOH
VOL
OEn
Output (B)
tPZH
Vm Vm
tPHZ
Vm
Output (B)
tPZL
tPLZ
Vm
VIH
0V
VVOY H
0V
VCC
VVOX L
Waveform 2 Output Enable and Disable Times
tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Figure 3. AC (Propagation Delay) Test Circuit Waveforms
Symbol
VmA
VmB
VX
VY
3.0 V – 4.5 V
VCCA/2
VCCB/2
VOL x 0.1
VOH x 0.9
2.3 V 2.7 V
VCCA/2
VCCB/2
VOL x 0.1
VOH x 0.9
VCC
1.65 V 1.95 V
VCCA/2
VCCB/2
VOL x 0.1
VOH x 0.9
1.4 V 1.6 V
VCCA/2
VCCB/2
VOL x 0.1
VOH x 0.9
0.9 V 1.3 V
VCCA/2
VCCB/2
VOL x 0.1
VOH x 0.9
http://onsemi.com
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