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PDF S6D0154 Data sheet ( Hoja de datos )
| Número de pieza | S6D0154 | |
| Descripción | MOBILE DISPLAY DRIVER IC | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de S6D0154 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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S6D0154
Rev. 1.10
MOBILE DISPLAY DRIVER IC
Property of Samsung Electronics Co., Ltd
Copyright © 2008 Samsung Electronics, Inc. All Rights Reserved
1 page  
Contents
Mobile Display Driver IC
1. Introduction............................................................................................. 12
1.1. Purpose of this document................................................................................................................... 12
1.2. Product options.................................................................................................................................... 12
2. Features................................................................................................... 13
3. Display Module Block Diagram.............................................................. 14
3.1. Signal flow of the display module and its relationship.................................................................... 14
3.2. Function Block Diagram and Signal Pads of S6D0154 .................................................................... 15
4. Chip Information ..................................................................................... 16
4.1. PAD Configuration ............................................................................................................................... 16
4.2. Bump PAD Information ....................................................................................................................... 17
4.3. ALIGN KEY CONFIGURATION AND COORDINATES ....................................................................... 19
5. IC Pad Description.................................................................................. 20
5.1. Pads for Power Supplies ..................................................................................................................... 20
5.2. Signal pads for Logic interface .......................................................................................................... 22
5.3. INTERFACE PAD CONFIGURATION .................................................................................................. 26
6. Electrical Specifications......................................................................... 27
6.1. Absolute Maximum Ratings................................................................................................................ 27
6.2. DC Characteristics ............................................................................................................................... 28
6.2.1. Basic Characteristics ....................................................................................................................... 28
6.3. AC characteristics................................................................................................................................ 30
6.4. Reset Input Timing............................................................................................................................... 34
6.5. MDDI IO DC/AC CHARACTERISTICS ................................................................................................. 35
6.6. External Power On/Off Sequence....................................................................................................... 37
6.6.1. External Power On Sequence ......................................................................................................... 37
6.6.2. External Power Off Sequence ......................................................................................................... 37
7. FUNCTIONAL DESCRIPTION ................................................................. 38
7.1. SYSTEM INTERFACE........................................................................................................................... 38
7.2. RGB INTERFACE.................................................................................................................................. 39
7.3. HIGH SPEED SERIAL INTERFACE (MDDI) ........................................................................................ 39
7.4. GRAPHICS RAM ................................................................................................................................... 39
7.5. PANEL INTERFACE CONTROLLER ................................................................................................... 39
7.6. GRAYSCALE VOLTAGE GENERATOR .............................................................................................. 39
7.7. OSCILLATION CIRCUIT (OSC)............................................................................................................ 39
7.8. SOURCE DRIVER ARRAY ................................................................................................................... 40
7.9. GATE DRIVER ARRAY......................................................................................................................... 40
7.10. GRAM ADDRESS MAP ...................................................................................................................... 40
8. PLUG & PLAY FUNCTION SPECIFICATION .......................................... 41
8.1. AC TIMING REQUIREMENTS .............................................................................................................. 41
8.2. POWER- UP SEQUENCE ..................................................................................................................... 43
8.3. POWER DOWN SEQUENCE................................................................................................................ 44
9. Instruction Sets....................................................................................... 45
9.1. Introduction .......................................................................................................................................... 45
9.2. Instruction Set ...................................................................................................................................... 46
9.3. Description of Instructions ................................................................................................................. 48
9.3.1. Index Register (IR) .......................................................................................................................... 48
9.3.2. Status Read..................................................................................................................................... 48
9.3.3. Version Management (R00h) .......................................................................................................... 48
9.3.4. Driver Output Control (R01h) .......................................................................................................... 49
9.3.5. LCD-Driving-Waveform Control (R02h) .......................................................................................... 53
9.3.6. Entry Mode (R03h) .......................................................................................................................... 56
9.3.7. Display Control (R07h) .................................................................................................................... 59
9.3.8. Blank Period Control 1 (R08h) ........................................................................................................ 61
9.3.9. Frame Cycle Control (R0Bh) ........................................................................................................... 62
9.3.10. External Display Interface Control (R0Ch) .................................................................................... 64
Page 5/194
2008-01-21
5 Page 
Mobile Display Driver IC
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Timing Diagram of 80-9bit CPU Interface ............................................................................... 117
Bit Assignment of Instructions on 80-8bit CPU Interface ........................................................ 118
Bit Assignment of GRAM Data on 80-8bit CPU Interface ....................................................... 118
Timing Diagram of 80-8bit CPU Interface ............................................................................... 118
Bit Assignment of Instructions on SPI ..................................................................................... 120
Bit Assignment of GRAM Data on SPI .................................................................................... 120
Basic Timing Diagram of Data Transfer through SPI .............................................................. 120
Timing Diagram of Consecutive Data-Write through SPI ........................................................ 120
Timing Diagram of Register / Status Read through SPI.......................................................... 121
Timing Diagram of GRAM-Data Read through SPI................................................................. 121
RGB Interface .......................................................................................................................... 122
Bit Assignment of GRAM Data on 18bit RGB Interface .......................................................... 123
Timing Diagram of 18/16bit RGB Interface ............................................................................. 123
Bit Assignment of GRAM Data on 16bit RGB Interface .......................................................... 124
Timing Diagram of 18/16bit RGB Interface ............................................................................. 124
Bit Assignment of GRAM Data on 6bit RGB Interface ............................................................ 125
Timing Diagram of 6bit RGB Interface..................................................................................... 125
Transfer Synchronization Function in 6-bit RGB Interface mode............................................ 126
GRAM Access through RGB Interface and SPI ...................................................................... 128
Transition between Internal Clock Operation Mode and External Clock Operation Mode...... 129
Physical connection of MDDI host and client .......................................................................... 130
Data-STB encoding ................................................................................................................. 130
Data / STB Generation & Recovery circuit .............................................................................. 131
Differential connection between host and client ...................................................................... 131
MDDI packet structure............................................................................................................. 132
Sub-frame header packet structure ......................................................................................... 133
Register access packet structure ............................................................................................ 133
Video stream packet structure................................................................................................. 134
Filler packet structure .............................................................................................................. 134
Link shutdown packet structure ............................................................................................... 134
Tearing-less display: data write speed is faster than display .................................................. 139
Tearing-less display: display speed is faster than data write .................................................. 139
MDDI Transceiver / Receiver state in hibernation................................................................... 140
Host-initiated link wakeup sequence ....................................................................................... 141
Client-initiated link wake-up sequence .................................................................................... 142
VSYNC based link wake-up procedure ................................................................................... 145
GPIO based link wake-up procedure....................................................................................... 146
Operating state in MDDI mode ................................................................................................ 148
Schematic diagram of sub panel control function.................................................................... 149
Main / Sub panel selection procedure ..................................................................................... 150
80mode 9/8 bit type register access data transfer .................................................................. 151
80 mode 9 bit video data transfer ............................................................................................ 151
80 mode 8 bit video data transfer ............................................................................................ 152
80 mode STN type convetional register instruction................................................................. 152
80 mode STN type included parameter................................................................................... 153
80 mode STN type 9 bit video data transfer............................................................................ 153
80 mode STN type 8bit video data transfer............................................................................. 154
Sub panel signal timing(80 mode)...................................................................................... 155
Sub panel signal timing(68 mode)...................................................................................... 156
Index/parameter write timing diagram ..................................................................................... 157
Image data write timing diagram ............................................................................................. 157
Change data path timing diagram ........................................................................................... 157
MDDI-integrated system structure........................................................................................... 158
Grayscale Control .................................................................................................................... 159
Structure of Grayscale Amplifier.............................................................................................. 160
Structure of Resistor Ladder Network 1 .................................................................................. 161
Structure of Resistor Ladder Network 2 .................................................................................. 162
The Operation of Adjusting Register ....................................................................................... 163
Relationship Between RAM Data , Source Output Voltage and VCOM (REV=0)................... 175
Relationship Between RAM Data , Source Output Voltage and VCOM (REV=1)................... 176
8-Color Display Control ........................................................................................................... 177
Setup Procedure For The 8-Color Mode ................................................................................. 178
DISPLAY ON / OFF SEQUENCE............................................................................................ 179
D-STAND-BY/STAND-BY SEQUENCE .................................................................................. 180
DEEP STAND-BY EXIT FLOW ............................................................................................... 180
Oscillation Circuit ..................................................................................................................... 181
Formula for the Frame Frequency........................................................................................... 182
Application Circuit Example..................................................................................................... 193
Page 11/194
2008-01-21
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet S6D0154.PDF ] | |
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