|
|
PDF 74ACTQ646 Data sheet ( Hoja de datos )
| Número de pieza | 74ACTQ646 | |
| Descripción | Quiet Series Octal Transceiver / Register | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 74ACTQ646 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
|
No Preview Available !
January 1990
Revised September 2000
74ACQ646 • 74ACTQ646
Quiet Series Octal Transceiver/Register
with 3-STATE Outputs
General Description
The ACQ/ACTQ646 consist of registered bus transceiver
circuits, with outputs, D-type flip-flops, and control circuitry
providing multiplexed transmission of data directly from the
input bus or from the internal storage registers. Data on the
A or B bus will be loaded into the respective registers on
the LOW-to-HIGH transition of the appropriate clock pin
(CPAB or CPBA). The four fundamental handling functions
available are illustrated in Figure 1, Figure 2, Figure 3 and
Figure 4.
The ACQ/ACTQ utilizes Fairchild Quiet Series technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series fea-
tures GTO output control and undershoot corrector in
addition to a split ground bus for superior performance.
Features
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Independent registers for A and B busses
s Multiplexed real-time and stored data transfers
s 300 mil slim dual-in-line package
s Outputs source/sink 24 mA
s Faster prop delays than the standard AC/ACT646
Ordering Code:
Order Number Package Number
Package Description
74ACQ646SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACQ464ASPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACTQ646SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACTQ464ASPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
A0–A7
B0–B7
CPAB, CPBA
SAB, SBA
G
DIR
Descriptions
Data Register A Inputs
Data Register A Outputs
Data Register B Inputs
Data Register B Outputs
Clock Pulse Inputs
Transmit/Receive Inputs
Output Enable Input
Direction Control Input
FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation
© 2000 Fairchild Semiconductor Corporation DS010635
www.fairchildsemi.com
1 page  
DC Electrical Characteristics for ACQ (Continued)
Symbol
Parameter
VCC
TA = +25°C
TA = −40°C to +85°C
Units
(V) Typ
Guaranteed Limits
Conditions
VOLV
VIHD
Quiet Output
Minimum Dynamic VOL
Minimum HIGH Level
Dynamic Input Voltage
5.0 −0.6 −1.2
5.0 3.1
3.5
Figures 5, 6
V
(Note 6)(Note 7)
V (Note 6)(Note 8)
VILD
Maximum LOW Level
Dynamic Input Voltage
5.0 1.9
1.5
V (Note 6)(Note 8)
Note 3: Maximum of 8 outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
Note 6: Plastic DIP package.
Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 5V. One output @ GND.
Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 5V (ACQ). Input-under-test switching 5V to threshold (VILD),
0V to threshold (VIHD) f = 1 MHz.
DC Electrical Characteristics for ACTQ
Symbol
Parameter
VCC
TA = +25°C
TA = −40°C to +85°C
Units
(V) Typ
Guaranteed Limits
Conditions
VIH Minimum HIGH Level
Input Voltage
VIL Maximum LOW Level
Input Voltage
VOH Minimum HIGH Level
Output Voltage
4.5 1.5
5.5 1.5
4.5 1.5
5.5 1.5
4.5 4.49
5.5 5.49
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
V VOUT = 0.1V
or VCC − 0.1V
V VOUT = 0.1V
or VCC − 0.1V
V IOUT = −50 µA
VOL Maximum LOW Level
Output Voltage
4.5 3.86
5.5 4.86
4.5 0.001
0.1
5.5 0.001
0.1
3.76
4.76
0.1
0.1
VIN = VIL or VIH
V IOH = −24 mA
IOH = −24 mA (Note 9)
V IOUT = 50 µA
4.5 0.36
5.5 0.36
IIN Maximum Input Leakage Current 5.5
±0.1
IOZT
Maximum I/O Leakage Current
5.5
(An, Bn Inputs)
±0.6
ICCT
Maximum ICC/Input
5.5 0.6
IOLD
Minimum Dynamic
5.5
IOHD
Output Current (Note 10)
5.5
ICC Maximum Quiescent
Supply Current
5.5
8.0
0.44
0.44
±1.0
±6.0
1.5
75
−75
80.0
VIN = VIL or VIH
V IOL = 24 mA
IOL = 24 mA (Note 9)
µA VI = VCC, GND
µA VI = VIL, VIH
VO = VCC, GND
mA VI = VCC − 2.1V
mA VOLD = 1.65V Max
mA VOHD = 3.85V Min
µA VIN = VCC
or GND
VOLP
VOLV
VIHD
Quiet Output
Maximum Dynamic VOL
Quiet Output
Minimum Dynamic VOL
Minimum HIGH Level
Dynamic Input Voltage
5.0 1.1
1.5
5.0 −0.6 −1.2
5.0 1.7
2.0
Figures 5, 6
V
(Note 11)(Note 12)
Figures 5, 6
V
(Note 11)(Note 12)
V (Note 11)(Note 13)
VILD
Maximum LOW Level
Dynamic Input Voltage
5.0 1.2
0.8
V (Note 11)(Note 13)
Note 9: All outputs loaded; thresholds on input associated with output under test.
Note 10: Maximum test duration 2.0 ms, one output loaded at a time.
Note 11: Plastic DIP Package.
Note 12: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.
Note 13: Max number of data inputs (n) switching. (n − 1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (VILD),
0V to threshold (VIHD), f = 1 MHz.
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74ACTQ646.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 74ACTQ646 | Quiet Series Octal Transceiver / Register | Fairchild Semiconductor |
| 74ACTQ646SC | Quiet Series Octal Transceiver/Register with 3-STATE Outputs | Fairchild Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |